vga_controller.fit.qmsg

基于VHDL语言关于VGA的简单应用。对于快速理解如何使用VGA有很大的帮助

{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0 0}  } {  } 0 0 "Finished register packing" 0 0 "" 0 0}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.383 ns register register " "Info: Estimated most critical path is register to register delay of 3.383 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns x\[0\] 1 REG LAB_X61_Y50 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X61_Y50; Fanout = 5; REG Node = 'x\[0\]'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { x[0] } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.648 ns) + CELL(0.621 ns) 1.269 ns Add0~121 2 COMB LAB_X61_Y50 2 " "Info: 2: + IC(0.648 ns) + CELL(0.621 ns) = 1.269 ns; Loc. = LAB_X61_Y50; Fanout = 2; COMB Node = 'Add0~121'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.269 ns" { x[0] Add0~121 } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.355 ns Add0~123 3 COMB LAB_X61_Y50 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.355 ns; Loc. = LAB_X61_Y50; Fanout = 2; COMB Node = 'Add0~123'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~121 Add0~123 } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.441 ns Add0~125 4 COMB LAB_X61_Y50 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.441 ns; Loc. = LAB_X61_Y50; Fanout = 2; COMB Node = 'Add0~125'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~123 Add0~125 } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.527 ns Add0~127 5 COMB LAB_X61_Y50 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.527 ns; Loc. = LAB_X61_Y50; Fanout = 2; COMB Node = 'Add0~127'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~125 Add0~127 } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.613 ns Add0~129 6 COMB LAB_X61_Y50 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.613 ns; Loc. = LAB_X61_Y50; Fanout = 2; COMB Node = 'Add0~129'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~127 Add0~129 } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.699 ns Add0~131 7 COMB LAB_X61_Y50 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.699 ns; Loc. = LAB_X61_Y50; Fanout = 2; COMB Node = 'Add0~131'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~129 Add0~131 } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.785 ns Add0~133 8 COMB LAB_X61_Y50 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.785 ns; Loc. = LAB_X61_Y50; Fanout = 2; COMB Node = 'Add0~133'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~131 Add0~133 } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.871 ns Add0~135 9 COMB LAB_X61_Y50 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 1.871 ns; Loc. = LAB_X61_Y50; Fanout = 2; COMB Node = 'Add0~135'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~133 Add0~135 } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.957 ns Add0~137 10 COMB LAB_X61_Y50 1 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 1.957 ns; Loc. = LAB_X61_Y50; Fanout = 1; COMB Node = 'Add0~137'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~135 Add0~137 } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 2.463 ns Add0~138 11 COMB LAB_X61_Y50 1 " "Info: 11: + IC(0.000 ns) + CELL(0.506 ns) = 2.463 ns; Loc. = LAB_X61_Y50; Fanout = 1; COMB Node = 'Add0~138'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { Add0~137 Add0~138 } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.161 ns) + CELL(0.651 ns) 3.275 ns x~275 12 COMB LAB_X61_Y50 1 " "Info: 12: + IC(0.161 ns) + CELL(0.651 ns) = 3.275 ns; Loc. = LAB_X61_Y50; Fanout = 1; COMB Node = 'x~275'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.812 ns" { Add0~138 x~275 } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.383 ns x\[9\] 13 REG LAB_X61_Y50 5 " "Info: 13: + IC(0.000 ns) + CELL(0.108 ns) = 3.383 ns; Loc. = LAB_X61_Y50; Fanout = 5; REG Node = 'x\[9\]'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { x~275 x[9] } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.574 ns ( 76.09 % ) " "Info: Total cell delay = 2.574 ns ( 76.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.809 ns ( 23.91 % ) " "Info: Total interconnect delay = 0.809 ns ( 23.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.383 ns" { x[0] Add0~121 Add0~123 Add0~125 Add0~127 Add0~129 Add0~131 Add0~133 Add0~135 Add0~137 Add0~138 x~275 x[9] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 0}