prev_cmp_vga_controller.tan.qmsg

基于VHDL语言关于VGA的简单应用。对于快速理解如何使用VGA有很大的帮助

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK_0 register x\[1\] register y\[2\] 262.26 MHz 3.813 ns Internal " "Info: Clock \"CLK_0\" has Internal fmax of 262.26 MHz between source register \"x\[1\]\" and destination register \"y\[2\]\" (period= 3.813 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.548 ns + Longest register register " "Info: + Longest register to register delay is 3.548 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns x\[1\] 1 REG LCFF_X61_Y50_N15 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X61_Y50_N15; Fanout = 6; REG Node = 'x\[1\]'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { x[1] } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.690 ns) + CELL(0.614 ns) 1.304 ns Equal0~94 2 COMB LCCOMB_X61_Y50_N8 1 " "Info: 2: + IC(0.690 ns) + CELL(0.614 ns) = 1.304 ns; Loc. = LCCOMB_X61_Y50_N8; Fanout = 1; COMB Node = 'Equal0~94'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.304 ns" { x[1] Equal0~94 } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.378 ns) + CELL(0.370 ns) 2.052 ns Equal0~95 3 COMB LCCOMB_X61_Y50_N10 12 " "Info: 3: + IC(0.378 ns) + CELL(0.370 ns) = 2.052 ns; Loc. = LCCOMB_X61_Y50_N10; Fanout = 12; COMB Node = 'Equal0~95'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.748 ns" { Equal0~94 Equal0~95 } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/tools/altera.quartusii.v8.0/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.641 ns) + CELL(0.855 ns) 3.548 ns y\[2\] 4 REG LCFF_X60_Y50_N11 3 " "Info: 4: + IC(0.641 ns) + CELL(0.855 ns) = 3.548 ns; Loc. = LCFF_X60_Y50_N11; Fanout = 3; REG Node = 'y\[2\]'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.496 ns" { Equal0~95 y[2] } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.839 ns ( 51.83 % ) " "Info: Total cell delay = 1.839 ns ( 51.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.709 ns ( 48.17 % ) " "Info: Total interconnect delay = 1.709 ns ( 48.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.548 ns" { x[1] Equal0~94 Equal0~95 y[2] } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "3.548 ns" { x[1] {} Equal0~94 {} Equal0~95 {} y[2] {} } { 0.000ns 0.690ns 0.378ns 0.641ns } { 0.000ns 0.614ns 0.370ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.001 ns - Smallest " "Info: - Smallest clock skew is -0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_0 destination 6.100 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK_0\" to destination register is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns CLK_0 1 CLK PIN_D16 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_D16; Fanout = 1; CLK Node = 'CLK_0'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_0 } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.970 ns) 2.981 ns CLK 2 REG LCFF_X47_Y50_N1 3 " "Info: 2: + IC(0.921 ns) + CELL(0.970 ns) = 2.981 ns; Loc. = LCFF_X47_Y50_N1; Fanout = 3; REG Node = 'CLK'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.891 ns" { CLK_0 CLK } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.000 ns) 3.987 ns CLK~clkctrl 3 COMB CLKCTRL_G11 26 " "Info: 3: + IC(1.006 ns) + CELL(0.000 ns) = 3.987 ns; Loc. = CLKCTRL_G11; Fanout = 26; COMB Node = 'CLK~clkctrl'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.006 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.447 ns) + CELL(0.666 ns) 6.100 ns y\[2\] 4 REG LCFF_X60_Y50_N11 3 " "Info: 4: + IC(1.447 ns) + CELL(0.666 ns) = 6.100 ns; Loc. = LCFF_X60_Y50_N11; Fanout = 3; REG Node = 'y\[2\]'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.113 ns" { CLK~clkctrl y[2] } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.726 ns ( 44.69 % ) " "Info: Total cell delay = 2.726 ns ( 44.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.374 ns ( 55.31 % ) " "Info: Total interconnect delay = 3.374 ns ( 55.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { CLK_0 CLK CLK~clkctrl y[2] } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { CLK_0 {} CLK_0~combout {} CLK {} CLK~clkctrl {} y[2] {} } { 0.000ns 0.000ns 0.921ns 1.006ns 1.447ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_0 source 6.101 ns - Longest register " "Info: - Longest clock path from clock \"CLK_0\" to source register is 6.101 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns CLK_0 1 CLK PIN_D16 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_D16; Fanout = 1; CLK Node = 'CLK_0'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_0 } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.970 ns) 2.981 ns CLK 2 REG LCFF_X47_Y50_N1 3 " "Info: 2: + IC(0.921 ns) + CELL(0.970 ns) = 2.981 ns; Loc. = LCFF_X47_Y50_N1; Fanout = 3; REG Node = 'CLK'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.891 ns" { CLK_0 CLK } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.000 ns) 3.987 ns CLK~clkctrl 3 COMB CLKCTRL_G11 26 " "Info: 3: + IC(1.006 ns) + CELL(0.000 ns) = 3.987 ns; Loc. = CLKCTRL_G11; Fanout = 26; COMB Node = 'CLK~clkctrl'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.006 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.448 ns) + CELL(0.666 ns) 6.101 ns x\[1\] 4 REG LCFF_X61_Y50_N15 6 " "Info: 4: + IC(1.448 ns) + CELL(0.666 ns) = 6.101 ns; Loc. = LCFF_X61_Y50_N15; Fanout = 6; REG Node = 'x\[1\]'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.114 ns" { CLK~clkctrl x[1] } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.726 ns ( 44.68 % ) " "Info: Total cell delay = 2.726 ns ( 44.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.375 ns ( 55.32 % ) " "Info: Total interconnect delay = 3.375 ns ( 55.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.101 ns" { CLK_0 CLK CLK~clkctrl x[1] } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "6.101 ns" { CLK_0 {} CLK_0~combout {} CLK {} CLK~clkctrl {} x[1] {} } { 0.000ns 0.000ns 0.921ns 1.006ns 1.448ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { CLK_0 CLK CLK~clkctrl y[2] } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { CLK_0 {} CLK_0~combout {} CLK {} CLK~clkctrl {} y[2] {} } { 0.000ns 0.000ns 0.921ns 1.006ns 1.447ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.101 ns" { CLK_0 CLK CLK~clkctrl x[1] } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "6.101 ns" { CLK_0 {} CLK_0~combout {} CLK {} CLK~clkctrl {} x[1] {} } { 0.000ns 0.000ns 0.921ns 1.006ns 1.448ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 62 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.548 ns" { x[1] Equal0~94 Equal0~95 y[2] } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "3.548 ns" { x[1] {} Equal0~94 {} Equal0~95 {} y[2] {} } { 0.000ns 0.690ns 0.378ns 0.641ns } { 0.000ns 0.614ns 0.370ns 0.855ns } "" } } { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { CLK_0 CLK CLK~clkctrl y[2] } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { CLK_0 {} CLK_0~combout {} CLK {} CLK~clkctrl {} y[2] {} } { 0.000ns 0.000ns 0.921ns 1.006ns 1.447ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.101 ns" { CLK_0 CLK CLK~clkctrl x[1] } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "6.101 ns" { CLK_0 {} CLK_0~combout {} CLK {} CLK~clkctrl {} x[1] {} } { 0.000ns 0.000ns 0.921ns 1.006ns 1.448ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK_0 oRed\[5\] vst 15.024 ns register " "Info: tco from clock \"CLK_0\" to destination pin \"oRed\[5\]\" through register \"vst\" is 15.024 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_0 source 6.100 ns + Longest register " "Info: + Longest clock path from clock \"CLK_0\" to source register is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns CLK_0 1 CLK PIN_D16 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_D16; Fanout = 1; CLK Node = 'CLK_0'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_0 } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.970 ns) 2.981 ns CLK 2 REG LCFF_X47_Y50_N1 3 " "Info: 2: + IC(0.921 ns) + CELL(0.970 ns) = 2.981 ns; Loc. = LCFF_X47_Y50_N1; Fanout = 3; REG Node = 'CLK'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.891 ns" { CLK_0 CLK } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.000 ns) 3.987 ns CLK~clkctrl 3 COMB CLKCTRL_G11 26 " "Info: 3: + IC(1.006 ns) + CELL(0.000 ns) = 3.987 ns; Loc. = CLKCTRL_G11; Fanout = 26; COMB Node = 'CLK~clkctrl'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.006 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.447 ns) + CELL(0.666 ns) 6.100 ns vst 4 REG LCFF_X60_Y50_N3 4 " "Info: 4: + IC(1.447 ns) + CELL(0.666 ns) = 6.100 ns; Loc. = LCFF_X60_Y50_N3; Fanout = 4; REG Node = 'vst'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.113 ns" { CLK~clkctrl vst } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.726 ns ( 44.69 % ) " "Info: Total cell delay = 2.726 ns ( 44.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.374 ns ( 55.31 % ) " "Info: Total interconnect delay = 3.374 ns ( 55.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { CLK_0 CLK CLK~clkctrl vst } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { CLK_0 {} CLK_0~combout {} CLK {} CLK~clkctrl {} vst {} } { 0.000ns 0.000ns 0.921ns 1.006ns 1.447ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.620 ns + Longest register pin " "Info: + Longest register to pin delay is 8.620 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vst 1 REG LCFF_X60_Y50_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X60_Y50_N3; Fanout = 4; REG Node = 'vst'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { vst } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.143 ns) + CELL(0.499 ns) 1.642 ns oRed~22 2 COMB LCCOMB_X62_Y50_N22 10 " "Info: 2: + IC(1.143 ns) + CELL(0.499 ns) = 1.642 ns; Loc. = LCCOMB_X62_Y50_N22; Fanout = 10; COMB Node = 'oRed~22'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.642 ns" { vst oRed~22 } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.772 ns) + CELL(3.206 ns) 8.620 ns oRed\[5\] 3 PIN PIN_G21 0 " "Info: 3: + IC(3.772 ns) + CELL(3.206 ns) = 8.620 ns; Loc. = PIN_G21; Fanout = 0; PIN Node = 'oRed\[5\]'" {  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.978 ns" { oRed~22 oRed[5] } "NODE_NAME" } } { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.705 ns ( 42.98 % ) " "Info: Total cell delay = 3.705 ns ( 42.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.915 ns ( 57.02 % ) " "Info: Total interconnect delay = 4.915 ns ( 57.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.620 ns" { vst oRed~22 oRed[5] } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "8.620 ns" { vst {} oRed~22 {} oRed[5] {} } { 0.000ns 1.143ns 3.772ns } { 0.000ns 0.499ns 3.206ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { CLK_0 CLK CLK~clkctrl vst } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { CLK_0 {} CLK_0~combout {} CLK {} CLK~clkctrl {} vst {} } { 0.000ns 0.000ns 0.921ns 1.006ns 1.447ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/tools/altera.quartusii.v8.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.620 ns" { vst oRed~22 oRed[5] } "NODE_NAME" } } { "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/tools/altera.quartusii.v8.0/quartus/bin/Technology_Viewer.qrui" "8.620 ns" { vst {} oRed~22 {} oRed[5] {} } { 0.000ns 1.143ns 3.772ns } { 0.000ns 0.499ns 3.206ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "128 " "Info: Peak virtual memory: 128 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 08 14:32:13 2008 " "Info: Processing ended: Sat Nov 08 14:32:13 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}