prev_cmp_vga_controller.tan.qmsg

基于VHDL语言关于VGA的简单应用。对于快速理解如何使用VGA有很大的帮助

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 08 14:32:11 2008 " "Info: Processing started: Sat Nov 08 14:32:11 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off VGA_Controller -c VGA_Controller --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off VGA_Controller -c VGA_Controller --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK_0 " "Info: Assuming node \"CLK_0\" is an undefined clock" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 20 -1 0 } } { "e:/tools/altera.quartusii.v8.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/tools/altera.quartusii.v8.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK_0" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CLK " "Info: Detected ripple clock \"CLK\" as buffer" {  } { { "VGA_Controller.vhd" "" { Text "E:/FPGA/vga1/VGA_Controller.vhd" 40 -1 0 } } { "e:/tools/altera.quartusii.v8.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/tools/altera.quartusii.v8.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}