vga_controller.map.rpt

基于VHDL语言关于VGA的简单应用。对于快速理解如何使用VGA有很大的帮助

; VGA_Controller.vhd               ; yes             ; User VHDL File  ; E:/FPGA/vga1/VGA_Controller.vhd ;
+----------------------------------+-----------------+-----------------+---------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 47    ;
;                                             ;       ;
; Total combinational functions               ; 47    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 14    ;
;     -- 3 input functions                    ; 9     ;
;     -- <=2 input functions                  ; 24    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 31    ;
;     -- arithmetic mode                      ; 16    ;
;                                             ;       ;
; Total registers                             ; 27    ;
;     -- Dedicated logic registers            ; 27    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 37    ;
; Maximum fan-out node                        ; CLK   ;
; Maximum fan-out                             ; 28    ;
; Total fan-out                               ; 247   ;
; Average fan-out                             ; 2.23  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |VGA_Controller            ; 47 (47)           ; 27 (27)      ; 0           ; 0            ; 0       ; 0         ; 37   ; 0            ; |VGA_Controller     ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-------------------------------------------------------------+
; Registers Removed During Synthesis                          ;
+----------------------------------------+--------------------+
; Register name                          ; Reason for Removal ;
+----------------------------------------+--------------------+
; bt[1..9]                               ; Merged with bt[0]  ;
; rt[0..8]                               ; Merged with rt[9]  ;
; gt[0..8]                               ; Merged with gt[9]  ;
; Total Number of Removed Registers = 27 ;                    ;
+----------------------------------------+--------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 27    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 26    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 8     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; hst                                    ; 4       ;
; vst                                    ; 4       ;
; Total number of inverted registers = 2 ;         ;
+----------------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Sat Nov 08 14:41:36 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off VGA_Controller -c VGA_Controller
Info: Found 2 design units, including 1 entities, in source file VGA_Controller.vhd
    Info: Found design unit 1: VGA_Controller-behave
    Info: Found entity 1: VGA_Controller
Info: Elaborating entity "VGA_Controller" for the top level hierarchy
Info: Duplicate registers merged to single register
    Info (13350): Duplicate register "bt[1]" merged to single register "bt[0]"
    Info (13350): Duplicate register "bt[2]" merged to single register "bt[0]"
    Info (13350): Duplicate register "bt[3]" merged to single register "bt[0]"
    Info (13350): Duplicate register "bt[4]" merged to single register "bt[0]"
    Info (13350): Duplicate register "bt[5]" merged to single register "bt[0]"
    Info (13350): Duplicate register "bt[6]" merged to single register "bt[0]"
    Info (13350): Duplicate register "bt[7]" merged to single register "bt[0]"
    Info (13350): Duplicate register "bt[8]" merged to single register "bt[0]"
    Info (13350): Duplicate register "bt[9]" merged to single register "bt[0]"
    Info (13350): Duplicate register "rt[0]" merged to single register "rt[9]"
    Info (13350): Duplicate register "rt[1]" merged to single register "rt[9]"
    Info (13350): Duplicate register "rt[2]" merged to single register "rt[9]"
    Info (13350): Duplicate register "rt[3]" merged to single register "rt[9]"
    Info (13350): Duplicate register "rt[4]" merged to single register "rt[9]"
    Info (13350): Duplicate register "rt[5]" merged to single register "rt[9]"
    Info (13350): Duplicate register "rt[6]" merged to single register "rt[9]"
    Info (13350): Duplicate register "rt[7]" merged to single register "rt[9]"
    Info (13350): Duplicate register "rt[8]" merged to single register "rt[9]"
    Info (13350): Duplicate register "gt[8]" merged to single register "gt[9]"
    Info (13350): Duplicate register "gt[7]" merged to single register "gt[9]"
    Info (13350): Duplicate register "gt[6]" merged to single register "gt[9]"
    Info (13350): Duplicate register "gt[5]" merged to single register "gt[9]"
    Info (13350): Duplicate register "gt[4]" merged to single register "gt[9]"
    Info (13350): Duplicate register "gt[3]" merged to single register "gt[9]"
    Info (13350): Duplicate register "gt[2]" merged to single register "gt[9]"
    Info (13350): Duplicate register "gt[1]" merged to single register "gt[9]"
    Info (13350): Duplicate register "gt[0]" merged to single register "gt[9]"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "BLANK" is stuck at VCC
    Warning (13410): Pin "SYNC" is stuck at VCC
Info: Implemented 84 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 35 output pins
    Info: Implemented 47 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 180 megabytes
    Info: Processing ended: Sat Nov 08 14:41:42 2008
    Info: Elapsed time: 00:00:06
    Info: Total CPU time (on all processors): 00:00:04