vga_controller.tan.rpt

基于VHDL语言关于VGA的简单应用。对于快速理解如何使用VGA有很大的帮助

; N/A   ; None         ; 12.530 ns  ; vst     ; oBlue[9]  ; CLK_0      ;
; N/A   ; None         ; 12.530 ns  ; vst     ; oBlue[8]  ; CLK_0      ;
; N/A   ; None         ; 12.530 ns  ; vst     ; oBlue[4]  ; CLK_0      ;
; N/A   ; None         ; 12.493 ns  ; hst     ; oBlue[5]  ; CLK_0      ;
; N/A   ; None         ; 12.493 ns  ; hst     ; oBlue[3]  ; CLK_0      ;
; N/A   ; None         ; 12.493 ns  ; hst     ; oBlue[2]  ; CLK_0      ;
; N/A   ; None         ; 12.492 ns  ; hst     ; oBlue[7]  ; CLK_0      ;
; N/A   ; None         ; 12.492 ns  ; hst     ; oBlue[6]  ; CLK_0      ;
; N/A   ; None         ; 12.483 ns  ; hst     ; oBlue[9]  ; CLK_0      ;
; N/A   ; None         ; 12.483 ns  ; hst     ; oBlue[8]  ; CLK_0      ;
; N/A   ; None         ; 12.483 ns  ; hst     ; oBlue[4]  ; CLK_0      ;
; N/A   ; None         ; 12.398 ns  ; bt[0]   ; oBlue[1]  ; CLK_0      ;
; N/A   ; None         ; 12.167 ns  ; rt[9]   ; oRed[8]   ; CLK_0      ;
; N/A   ; None         ; 12.167 ns  ; rt[9]   ; oRed[7]   ; CLK_0      ;
; N/A   ; None         ; 11.937 ns  ; hs~reg0 ; hs        ; CLK_0      ;
; N/A   ; None         ; 11.679 ns  ; bt[0]   ; oBlue[5]  ; CLK_0      ;
; N/A   ; None         ; 11.679 ns  ; bt[0]   ; oBlue[3]  ; CLK_0      ;
; N/A   ; None         ; 11.679 ns  ; bt[0]   ; oBlue[2]  ; CLK_0      ;
; N/A   ; None         ; 11.678 ns  ; bt[0]   ; oBlue[7]  ; CLK_0      ;
; N/A   ; None         ; 11.678 ns  ; bt[0]   ; oBlue[6]  ; CLK_0      ;
; N/A   ; None         ; 11.669 ns  ; bt[0]   ; oBlue[9]  ; CLK_0      ;
; N/A   ; None         ; 11.669 ns  ; bt[0]   ; oBlue[8]  ; CLK_0      ;
; N/A   ; None         ; 11.669 ns  ; bt[0]   ; oBlue[4]  ; CLK_0      ;
; N/A   ; None         ; 11.603 ns  ; vs~reg0 ; vs        ; CLK_0      ;
; N/A   ; None         ; 9.225 ns   ; CLK     ; VGA_CLK   ; CLK_0      ;
+-------+--------------+------------+---------+-----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Sat Nov 08 14:42:23 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off VGA_Controller -c VGA_Controller --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK_0" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "CLK" as buffer
Info: Clock "CLK_0" has Internal fmax of 262.26 MHz between source register "x[1]" and destination register "y[2]" (period= 3.813 ns)
    Info: + Longest register to register delay is 3.548 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X61_Y50_N15; Fanout = 6; REG Node = 'x[1]'
        Info: 2: + IC(0.690 ns) + CELL(0.614 ns) = 1.304 ns; Loc. = LCCOMB_X61_Y50_N8; Fanout = 1; COMB Node = 'Equal0~94'
        Info: 3: + IC(0.378 ns) + CELL(0.370 ns) = 2.052 ns; Loc. = LCCOMB_X61_Y50_N10; Fanout = 12; COMB Node = 'Equal0~95'
        Info: 4: + IC(0.641 ns) + CELL(0.855 ns) = 3.548 ns; Loc. = LCFF_X60_Y50_N11; Fanout = 3; REG Node = 'y[2]'
        Info: Total cell delay = 1.839 ns ( 51.83 % )
        Info: Total interconnect delay = 1.709 ns ( 48.17 % )
    Info: - Smallest clock skew is -0.001 ns
        Info: + Shortest clock path from clock "CLK_0" to destination register is 6.100 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_D16; Fanout = 1; CLK Node = 'CLK_0'
            Info: 2: + IC(0.921 ns) + CELL(0.970 ns) = 2.981 ns; Loc. = LCFF_X47_Y50_N1; Fanout = 3; REG Node = 'CLK'
            Info: 3: + IC(1.006 ns) + CELL(0.000 ns) = 3.987 ns; Loc. = CLKCTRL_G11; Fanout = 26; COMB Node = 'CLK~clkctrl'
            Info: 4: + IC(1.447 ns) + CELL(0.666 ns) = 6.100 ns; Loc. = LCFF_X60_Y50_N11; Fanout = 3; REG Node = 'y[2]'
            Info: Total cell delay = 2.726 ns ( 44.69 % )
            Info: Total interconnect delay = 3.374 ns ( 55.31 % )
        Info: - Longest clock path from clock "CLK_0" to source register is 6.101 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_D16; Fanout = 1; CLK Node = 'CLK_0'
            Info: 2: + IC(0.921 ns) + CELL(0.970 ns) = 2.981 ns; Loc. = LCFF_X47_Y50_N1; Fanout = 3; REG Node = 'CLK'
            Info: 3: + IC(1.006 ns) + CELL(0.000 ns) = 3.987 ns; Loc. = CLKCTRL_G11; Fanout = 26; COMB Node = 'CLK~clkctrl'
            Info: 4: + IC(1.448 ns) + CELL(0.666 ns) = 6.101 ns; Loc. = LCFF_X61_Y50_N15; Fanout = 6; REG Node = 'x[1]'
            Info: Total cell delay = 2.726 ns ( 44.68 % )
            Info: Total interconnect delay = 3.375 ns ( 55.32 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "CLK_0" to destination pin "oRed[5]" through register "vst" is 15.024 ns
    Info: + Longest clock path from clock "CLK_0" to source register is 6.100 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_D16; Fanout = 1; CLK Node = 'CLK_0'
        Info: 2: + IC(0.921 ns) + CELL(0.970 ns) = 2.981 ns; Loc. = LCFF_X47_Y50_N1; Fanout = 3; REG Node = 'CLK'
        Info: 3: + IC(1.006 ns) + CELL(0.000 ns) = 3.987 ns; Loc. = CLKCTRL_G11; Fanout = 26; COMB Node = 'CLK~clkctrl'
        Info: 4: + IC(1.447 ns) + CELL(0.666 ns) = 6.100 ns; Loc. = LCFF_X60_Y50_N3; Fanout = 4; REG Node = 'vst'
        Info: Total cell delay = 2.726 ns ( 44.69 % )
        Info: Total interconnect delay = 3.374 ns ( 55.31 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 8.620 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X60_Y50_N3; Fanout = 4; REG Node = 'vst'
        Info: 2: + IC(1.143 ns) + CELL(0.499 ns) = 1.642 ns; Loc. = LCCOMB_X62_Y50_N22; Fanout = 10; COMB Node = 'oRed~22'
        Info: 3: + IC(3.772 ns) + CELL(3.206 ns) = 8.620 ns; Loc. = PIN_G21; Fanout = 0; PIN Node = 'oRed[5]'
        Info: Total cell delay = 3.705 ns ( 42.98 % )
        Info: Total interconnect delay = 4.915 ns ( 57.02 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 128 megabytes
    Info: Processing ended: Sat Nov 08 14:42:25 2008
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01