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📄 stm32f10x_spi.s

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///////////////////////////////////////////////////////////////////////////////
//                                                                            /
//                                                      30/Jul/2008  14:37:40 /
// IAR ARM ANSI C/C++ Compiler V5.11.0.20622/W32 EVALUATION                   /
// Copyright 1999-2007 IAR Systems. All rights reserved.                      /
//                                                                            /
//    Cpu mode     =  thumb                                                   /
//    Endian       =  little                                                  /
//    Source file  =  E:\library\src\stm32f10x_spi.c                          /
//    Command line =  E:\library\src\stm32f10x_spi.c -D EMB_FLASH -lCN        /
//                    E:\ELE\yten\pro\Debug\List\ -lb                         /
//                    E:\ELE\yten\pro\Debug\List\ -o                          /
//                    E:\ELE\yten\pro\Debug\Obj\ --no_cse --no_unroll         /
//                    --no_inline --no_code_motion --no_tbaa --no_clustering  /
//                    --no_scheduling --debug --endian little --cpu           /
//                    Cortex-M3 -e --fpu None --dlib_config "C:\Program       /
//                    Files\IAR Systems\Embedded Workbench 5.0                /
//                    Evaluation\ARM\INC\DLib_Config_Normal.h" -I             /
//                    E:\ELE\yten\pro\ -I E:\ELE\yten\pro\..\LIBRARY\INC\ -I  /
//                    "C:\Program Files\IAR Systems\Embedded Workbench 5.0    /
//                    Evaluation\ARM\INC\" --section .text=.XML -On           /
//    List file    =  E:\ELE\yten\pro\Debug\List\stm32f10x_spi.s              /
//                                                                            /
//                                                                            /
///////////////////////////////////////////////////////////////////////////////

        NAME stm32f10x_spi

        EXTERN RCC_APB1PeriphResetCmd
        EXTERN RCC_APB2PeriphResetCmd

        PUBLIC SPI_BiDirectionalLineConfig
        PUBLIC SPI_CalculateCRC
        PUBLIC SPI_ClearFlag
        PUBLIC SPI_ClearITPendingBit
        PUBLIC SPI_Cmd
        PUBLIC SPI_DMACmd
        PUBLIC SPI_DataSizeConfig
        PUBLIC SPI_DeInit
        PUBLIC SPI_GetCRC
        PUBLIC SPI_GetCRCPolynomial
        PUBLIC SPI_GetFlagStatus
        PUBLIC SPI_GetITStatus
        PUBLIC SPI_ITConfig
        PUBLIC SPI_Init
        PUBLIC SPI_NSSInternalSoftwareConfig
        PUBLIC SPI_ReceiveData
        PUBLIC SPI_SSOutputCmd
        PUBLIC SPI_SendData
        PUBLIC SPI_StructInit
        PUBLIC SPI_TransmitCRC


        SECTION `.XML`:CODE:NOROOT(2)
        THUMB
SPI_DeInit:
        PUSH     {R4,LR}
        MOVS     R4,R0
        MOVS     R0,R4
        LDR.N    R1,??SPI_DeInit_0  ;; 0x40003800
        SUBS     R0,R0,R1
        BEQ.N    ??SPI_DeInit_1
        MOVS     R1,#+63488
        SUBS     R0,R0,R1
        BNE.N    ??SPI_DeInit_2
??SPI_DeInit_3:
        MOVS     R1,#+1
        MOVS     R0,#+4096
        BL       RCC_APB2PeriphResetCmd
        MOVS     R1,#+0
        MOVS     R0,#+4096
        BL       RCC_APB2PeriphResetCmd
        B.N      ??SPI_DeInit_2
??SPI_DeInit_1:
        MOVS     R1,#+1
        MOVS     R0,#+16384
        BL       RCC_APB1PeriphResetCmd
        MOVS     R1,#+0
        MOVS     R0,#+16384
        BL       RCC_APB1PeriphResetCmd
??SPI_DeInit_2:
        POP      {R4,PC}          ;; return
        DATA
??SPI_DeInit_0:
        DC32     0x40003800

        SECTION `.XML`:CODE:NOROOT(2)
        THUMB
SPI_Init:
        PUSH     {R4,R5}
        MOVS     R2,#+0
        MOVS     R3,R2
        LDRH     R2,[R0, #+0]
        MOVS     R3,R2
        ANDS     R3,R3,#0x3040
        MOVS     R2,R3
        LDRH     R3,[R1, #+0]
        LDRH     R4,[R1, #+2]
        ORRS     R4,R4,R3
        LDRH     R3,[R1, #+4]
        ORRS     R3,R3,R4
        LDRH     R4,[R1, #+6]
        ORRS     R4,R4,R3
        LDRH     R3,[R1, #+8]
        ORRS     R3,R3,R4
        LDRH     R4,[R1, #+10]
        ORRS     R4,R4,R3
        LDRH     R5,[R1, #+12]
        ORRS     R5,R5,R4
        LDRH     R3,[R1, #+14]
        ORRS     R3,R3,R5
        ORRS     R3,R3,R2
        STRH     R3,[R0, #+0]
        LDRH     R2,[R1, #+16]
        STRH     R2,[R0, #+16]
        POP      {R4,R5}
        BX       LR               ;; return

        SECTION `.XML`:CODE:NOROOT(2)
        THUMB
SPI_StructInit:
        MOVS     R1,#+0
        STRH     R1,[R0, #+0]
        MOVS     R1,#+0
        STRH     R1,[R0, #+2]
        MOVS     R1,#+0
        STRH     R1,[R0, #+4]
        MOVS     R1,#+0
        STRH     R1,[R0, #+6]
        MOVS     R1,#+0
        STRH     R1,[R0, #+8]
        MOVS     R1,#+0
        STRH     R1,[R0, #+10]
        MOVS     R1,#+0
        STRH     R1,[R0, #+12]
        MOVS     R1,#+0
        STRH     R1,[R0, #+14]
        MOVS     R1,#+7
        STRH     R1,[R0, #+16]
        BX       LR               ;; return

        SECTION `.XML`:CODE:NOROOT(2)
        THUMB
SPI_Cmd:
        UXTB     R1,R1            ;; ZeroExtS R1,R1,#+24,#+24
        CMP      R1,#+0
        BEQ.N    ??SPI_Cmd_0
        LDRH     R2,[R0, #+0]
        ORRS     R2,R2,#0x40
        STRH     R2,[R0, #+0]
        B.N      ??SPI_Cmd_1
??SPI_Cmd_0:
        LDRH     R2,[R0, #+0]
        LDR.N    R3,??SPI_Cmd_2   ;; 0xffbf
        ANDS     R3,R3,R2
        STRH     R3,[R0, #+0]
??SPI_Cmd_1:
        BX       LR               ;; return
        Nop      
        DATA
??SPI_Cmd_2:
        DC32     0xffbf

        SECTION `.XML`:CODE:NOROOT(2)
        THUMB
SPI_ITConfig:
        PUSH     {R4,R5}
        MOVS     R5,#+0
        MOVS     R3,R5
        MOVS     R5,#+0
        MOVS     R4,R5
        UXTB     R1,R1            ;; ZeroExtS R1,R1,#+24,#+24
        LSRS     R5,R1,#+4
        UXTB     R5,R5            ;; ZeroExtS R5,R5,#+24,#+24
        MOVS     R3,R5
        MOVS     R5,#+1
        LSLS     R5,R5,R3
        MOVS     R4,R5
        UXTB     R2,R2            ;; ZeroExtS R2,R2,#+24,#+24
        CMP      R2,#+0
        BEQ.N    ??SPI_ITConfig_0
        LDRH     R5,[R0, #+4]
        ORRS     R5,R5,R4
        STRH     R5,[R0, #+4]
        B.N      ??SPI_ITConfig_1
??SPI_ITConfig_0:
        LDRH     R5,[R0, #+4]
        BICS     R5,R5,R4
        STRH     R5,[R0, #+4]
??SPI_ITConfig_1:
        POP      {R4,R5}
        BX       LR               ;; return

        SECTION `.XML`:CODE:NOROOT(2)
        THUMB
SPI_DMACmd:
        UXTB     R2,R2            ;; ZeroExtS R2,R2,#+24,#+24
        CMP      R2,#+0
        BEQ.N    ??SPI_DMACmd_0
        LDRH     R3,[R0, #+4]
        ORRS     R3,R3,R1
        STRH     R3,[R0, #+4]
        B.N      ??SPI_DMACmd_1
??SPI_DMACmd_0:
        LDRH     R3,[R0, #+4]
        BICS     R3,R3,R1
        STRH     R3,[R0, #+4]
??SPI_DMACmd_1:
        BX       LR               ;; return

        SECTION `.XML`:CODE:NOROOT(2)
        THUMB
SPI_SendData:
        STRH     R1,[R0, #+12]
        BX       LR               ;; return

        SECTION `.XML`:CODE:NOROOT(2)
        THUMB
SPI_ReceiveData:
        LDRH     R0,[R0, #+12]
        BX       LR               ;; return

        SECTION `.XML`:CODE:NOROOT(2)
        THUMB
SPI_NSSInternalSoftwareConfig:
        LDR.N    R2,??SPI_NSSInternalSoftwareConfig_0  ;; 0xfeff
        UXTH     R1,R1            ;; ZeroExtS R1,R1,#+16,#+16
        CMP      R1,R2
        BEQ.N    ??SPI_NSSInternalSoftwareConfig_1
        LDRH     R2,[R0, #+0]
        ORRS     R2,R2,#0x100
        STRH     R2,[R0, #+0]
        B.N      ??SPI_NSSInternalSoftwareConfig_2
??SPI_NSSInternalSoftwareConfig_1:
        LDRH     R2,[R0, #+0]
        LDR.N    R3,??SPI_NSSInternalSoftwareConfig_0  ;; 0xfeff
        ANDS     R3,R3,R2
        STRH     R3,[R0, #+0]
??SPI_NSSInternalSoftwareConfig_2:
        BX       LR               ;; return
        DATA
??SPI_NSSInternalSoftwareConfig_0:
        DC32     0xfeff

        SECTION `.XML`:CODE:NOROOT(2)
        THUMB
SPI_SSOutputCmd:

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