📄 stm32f10x_rcc.lst
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422 * - RCC_HCLK_Div2: APB1 clock = HCLK/2
423 * - RCC_HCLK_Div4: APB1 clock = HCLK/4
424 * - RCC_HCLK_Div8: APB1 clock = HCLK/8
425 * - RCC_HCLK_Div16: APB1 clock = HCLK/16
426 * Output : None
427 * Return : None
428 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
429 void RCC_PCLK1Config(u32 RCC_PCLK1)
430 {
431 u32 tmpreg = 0;
\ RCC_PCLK1Config:
\ 00000000 0022 MOVS R2,#+0
\ 00000002 1100 MOVS R1,R2
432
433 /* Check the parameters */
434 assert_param(IS_RCC_PCLK(RCC_PCLK1));
435
436 tmpreg = RCC->CFGR;
\ 00000004 .... LDR.N R2,??DataTable38 ;; 0x40021004
\ 00000006 1268 LDR R2,[R2, #+0]
\ 00000008 1100 MOVS R1,R2
437
438 /* Clear PPRE1[10:8] bits */
439 tmpreg &= CFGR_PPRE1_Reset_Mask;
\ 0000000A 0A00 MOVS R2,R1
\ 0000000C 7FF4E061 MVNS R1,#+1792
\ 00000010 1140 ANDS R1,R1,R2
440
441 /* Set PPRE1[10:8] bits according to RCC_PCLK1 value */
442 tmpreg |= RCC_PCLK1;
\ 00000012 0143 ORRS R1,R1,R0
443
444 /* Store the new value */
445 RCC->CFGR = tmpreg;
\ 00000014 .... LDR.N R2,??DataTable38 ;; 0x40021004
\ 00000016 1160 STR R1,[R2, #+0]
446 }
\ 00000018 7047 BX LR ;; return
447
448 /*******************************************************************************
449 * Function Name : RCC_PCLK2Config
450 * Description : Configures the High Speed APB clock (PCLK2).
451 * Input : - RCC_PCLK2: defines the APB2 clock. This clock is derived
452 * from the AHB clock (HCLK).
453 * This parameter can be one of the following values:
454 * - RCC_HCLK_Div1: APB2 clock = HCLK
455 * - RCC_HCLK_Div2: APB2 clock = HCLK/2
456 * - RCC_HCLK_Div4: APB2 clock = HCLK/4
457 * - RCC_HCLK_Div8: APB2 clock = HCLK/8
458 * - RCC_HCLK_Div16: APB2 clock = HCLK/16
459 * Output : None
460 * Return : None
461 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
462 void RCC_PCLK2Config(u32 RCC_PCLK2)
463 {
464 u32 tmpreg = 0;
\ RCC_PCLK2Config:
\ 00000000 0022 MOVS R2,#+0
\ 00000002 1100 MOVS R1,R2
465
466 /* Check the parameters */
467 assert_param(IS_RCC_PCLK(RCC_PCLK2));
468
469 tmpreg = RCC->CFGR;
\ 00000004 .... LDR.N R2,??DataTable38 ;; 0x40021004
\ 00000006 1268 LDR R2,[R2, #+0]
\ 00000008 1100 MOVS R1,R2
470
471 /* Clear PPRE2[13:11] bits */
472 tmpreg &= CFGR_PPRE2_Reset_Mask;
\ 0000000A 0A00 MOVS R2,R1
\ 0000000C 7FF46051 MVNS R1,#+14336
\ 00000010 1140 ANDS R1,R1,R2
473
474 /* Set PPRE2[13:11] bits according to RCC_PCLK2 value */
475 tmpreg |= RCC_PCLK2 << 3;
\ 00000012 51EAC001 ORRS R1,R1,R0, LSL #+3
476
477 /* Store the new value */
478 RCC->CFGR = tmpreg;
\ 00000016 .... LDR.N R2,??DataTable38 ;; 0x40021004
\ 00000018 1160 STR R1,[R2, #+0]
479 }
\ 0000001A 7047 BX LR ;; return
480
481 /*******************************************************************************
482 * Function Name : RCC_ITConfig
483 * Description : Enables or disables the specified RCC interrupts.
484 * Input : - RCC_IT: specifies the RCC interrupt sources to be enabled
485 * or disabled.
486 * This parameter can be any combination of the following values:
487 * - RCC_IT_LSIRDY: LSI ready interrupt
488 * - RCC_IT_LSERDY: LSE ready interrupt
489 * - RCC_IT_HSIRDY: HSI ready interrupt
490 * - RCC_IT_HSERDY: HSE ready interrupt
491 * - RCC_IT_PLLRDY: PLL ready interrupt
492 * - NewState: new state of the specified RCC interrupts.
493 * This parameter can be: ENABLE or DISABLE.
494 * Output : None
495 * Return : None
496 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
497 void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState)
498 {
499 /* Check the parameters */
500 assert_param(IS_RCC_IT(RCC_IT));
501 assert_param(IS_FUNCTIONAL_STATE(NewState));
502
503 if (NewState != DISABLE)
\ RCC_ITConfig:
\ 00000000 C9B2 UXTB R1,R1 ;; ZeroExtS R1,R1,#+24,#+24
\ 00000002 0029 CMP R1,#+0
\ 00000004 05D0 BEQ.N ??RCC_ITConfig_0
504 {
505 /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
506 *(vu8 *) 0x40021009 |= RCC_IT;
\ 00000006 064A LDR.N R2,??RCC_ITConfig_1 ;; 0x40021009
\ 00000008 1278 LDRB R2,[R2, #+0]
\ 0000000A 0243 ORRS R2,R2,R0
\ 0000000C 044B LDR.N R3,??RCC_ITConfig_1 ;; 0x40021009
\ 0000000E 1A70 STRB R2,[R3, #+0]
\ 00000010 04E0 B.N ??RCC_ITConfig_2
507 }
508 else
509 {
510 /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
511 *(vu8 *) 0x40021009 &= ~(u32)RCC_IT;
\ ??RCC_ITConfig_0:
\ 00000012 034A LDR.N R2,??RCC_ITConfig_1 ;; 0x40021009
\ 00000014 1278 LDRB R2,[R2, #+0]
\ 00000016 8243 BICS R2,R2,R0
\ 00000018 014B LDR.N R3,??RCC_ITConfig_1 ;; 0x40021009
\ 0000001A 1A70 STRB R2,[R3, #+0]
512 }
513 }
\ ??RCC_ITConfig_2:
\ 0000001C 7047 BX LR ;; return
\ 0000001E 00BF Nop
\ ??RCC_ITConfig_1:
\ 00000020 09100240 DC32 0x40021009
514
515 /*******************************************************************************
516 * Function Name : RCC_USBCLKConfig
517 * Description : Configures the USB clock (USBCLK).
518 * Input : - RCC_USBCLKSource: specifies the USB clock source. This clock
519 * is derived from the PLL output.
520 * This parameter can be one of the following values:
521 * - RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5
522 * selected as USB clock source
523 * - RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB
524 * clock source
525 * Output : None
526 * Return : None
527 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
528 void RCC_USBCLKConfig(u32 RCC_USBCLKSource)
529 {
530 /* Check the parameters */
531 assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
532
533 *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;
\ RCC_USBCLKConfig:
\ 00000000 0149 LDR.N R1,??RCC_USBCLKConfig_0 ;; 0x424200d8
\ 00000002 0860 STR R0,[R1, #+0]
534 }
\ 00000004 7047 BX LR ;; return
\ 00000006 00BF Nop
\ ??RCC_USBCLKConfig_0:
\ 00000008 D8004242 DC32 0x424200d8
535
536 /*******************************************************************************
537 * Function Name : RCC_ADCCLKConfig
538 * Description : Configures the ADC clock (ADCCLK).
539 * Input : - RCC_ADCCLK: defines the ADC clock. This clock is derived
540 * from the APB2 clock (PCLK2).
541 * This parameter can be one of the following values:
542 * - RCC_PCLK2_Div2: ADC clock = PCLK2/2
543 * - RCC_PCLK2_Div4: ADC clock = PCLK2/4
544 * - RCC_PCLK2_Div6: ADC clock = PCLK2/6
545 * - RCC_PCLK2_Div8: ADC clock = PCLK2/8
546 * Output : None
547 * Return : None
548 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
549 void RCC_ADCCLKConfig(u32 RCC_ADCCLK)
550 {
551 u32 tmpreg = 0;
\ RCC_ADCCLKConfig:
\ 00000000 0022 MOVS R2,#+0
\ 00000002 1100 MOVS R1,R2
552
553 /* Check the parameters */
554 assert_param(IS_RCC_ADCCLK(RCC_ADCCLK));
555
556 tmpreg = RCC->CFGR;
\ 00000004 .... LDR.N R2,??DataTable38 ;; 0x40021004
\ 00000006 1268 LDR R2,[R2, #+0]
\ 00000008 1100 MOVS R1,R2
557
558 /* Clear ADCPRE[15:14] bits */
559 tmpreg &= CFGR_ADCPRE_Reset_Mask;
\ 0000000A 0A00 MOVS R2,R1
\ 0000000C 7FF44041 MVNS R1,#+49152
\ 00000010 1140 ANDS R1,R1,R2
560
561 /* Set ADCPRE[15:14] bits according to RCC_ADCCLK value */
562 tmpreg |= RCC_ADCCLK;
\ 00000012 0143 ORRS R1,R1,R0
563
564 /* Store the new value */
565 RCC->CFGR = tmpreg;
\ 00000014 .... LDR.N R2,??DataTable38 ;; 0x40021004
\ 00000016 1160 STR R1,[R2, #+0]
566 }
\ 00000018 7047 BX LR ;; return
567
568 /*******************************************************************************
569 * Function Name : RCC_LSEConfig
570 * Description : Configures the External Low Speed oscillator (LSE).
571 * Input : - RCC_LSE: specifies the new state of the LSE.
572 * This parameter can be one of the following values:
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