📄 stm32f10x_rcc.lst
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265 * This parameter can be: ENABLE or DISABLE.
266 * Output : None
267 * Return : None
268 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
269 void RCC_HSICmd(FunctionalState NewState)
270 {
271 /* Check the parameters */
272 assert_param(IS_FUNCTIONAL_STATE(NewState));
273
274 *(vu32 *) CR_HSION_BB = (u32)NewState;
\ RCC_HSICmd:
\ 00000000 0149 LDR.N R1,??RCC_HSICmd_0 ;; 0x42420000
\ 00000002 C0B2 UXTB R0,R0 ;; ZeroExtS R0,R0,#+24,#+24
\ 00000004 0860 STR R0,[R1, #+0]
275
276 }
\ 00000006 7047 BX LR ;; return
\ ??RCC_HSICmd_0:
\ 00000008 00004242 DC32 0x42420000
277
278 /*******************************************************************************
279 * Function Name : RCC_PLLConfig
280 * Description : Configures the PLL clock source and multiplication factor.
281 * This function must be used only when the PLL is disabled.
282 * Input : - RCC_PLLSource: specifies the PLL entry clock source.
283 * This parameter can be one of the following values:
284 * - RCC_PLLSource_HSI_Div2: HSI oscillator clock divided
285 * by 2 selected as PLL clock entry
286 * - RCC_PLLSource_HSE_Div1: HSE oscillator clock selected
287 * as PLL clock entry
288 * - RCC_PLLSource_HSE_Div2: HSE oscillator clock divided
289 * by 2 selected as PLL clock entry
290 * - RCC_PLLMul: specifies the PLL multiplication factor.
291 * This parameter can be RCC_PLLMul_x where x:[2,16]
292 * Output : None
293 * Return : None
294 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
295 void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul)
296 {
297 u32 tmpreg = 0;
\ RCC_PLLConfig:
\ 00000000 0023 MOVS R3,#+0
\ 00000002 1A00 MOVS R2,R3
298
299 /* Check the parameters */
300 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
301 assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
302
303 tmpreg = RCC->CFGR;
\ 00000004 .... LDR.N R3,??DataTable38 ;; 0x40021004
\ 00000006 1B68 LDR R3,[R3, #+0]
\ 00000008 1A00 MOVS R2,R3
304
305 /* Clear PLLSRC, PLLXTPRE and PLLMUL[21:18] bits */
306 tmpreg &= CFGR_PLL_Mask;
\ 0000000A 1300 MOVS R3,R2
\ 0000000C 7FF47C12 MVNS R2,#+4128768
\ 00000010 1A40 ANDS R2,R2,R3
307
308 /* Set the PLL configuration bits */
309 tmpreg |= RCC_PLLSource | RCC_PLLMul;
\ 00000012 1300 MOVS R3,R2
\ 00000014 0A00 MOVS R2,R1
\ 00000016 0243 ORRS R2,R2,R0
\ 00000018 1A43 ORRS R2,R2,R3
310
311 /* Store the new value */
312 RCC->CFGR = tmpreg;
\ 0000001A .... LDR.N R3,??DataTable38 ;; 0x40021004
\ 0000001C 1A60 STR R2,[R3, #+0]
313 }
\ 0000001E 7047 BX LR ;; return
314
315 /*******************************************************************************
316 * Function Name : RCC_PLLCmd
317 * Description : Enables or disables the PLL.
318 * The PLL can not be disabled if it is used as system clock.
319 * Input : - NewState: new state of the PLL.
320 * This parameter can be: ENABLE or DISABLE.
321 * Output : None
322 * Return : None
323 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
324 void RCC_PLLCmd(FunctionalState NewState)
325 {
326 /* Check the parameters */
327 assert_param(IS_FUNCTIONAL_STATE(NewState));
328
329 *(vu32 *) CR_PLLON_BB = (u32)NewState;
\ RCC_PLLCmd:
\ 00000000 0149 LDR.N R1,??RCC_PLLCmd_0 ;; 0x42420060
\ 00000002 C0B2 UXTB R0,R0 ;; ZeroExtS R0,R0,#+24,#+24
\ 00000004 0860 STR R0,[R1, #+0]
330 }
\ 00000006 7047 BX LR ;; return
\ ??RCC_PLLCmd_0:
\ 00000008 60004242 DC32 0x42420060
331
332 /*******************************************************************************
333 * Function Name : RCC_SYSCLKConfig
334 * Description : Configures the system clock (SYSCLK).
335 * Input : - RCC_SYSCLKSource: specifies the clock source used as system
336 * clock. This parameter can be one of the following values:
337 * - RCC_SYSCLKSource_HSI: HSI selected as system clock
338 * - RCC_SYSCLKSource_HSE: HSE selected as system clock
339 * - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
340 * Output : None
341 * Return : None
342 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
343 void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource)
344 {
345 u32 tmpreg = 0;
\ RCC_SYSCLKConfig:
\ 00000000 0022 MOVS R2,#+0
\ 00000002 1100 MOVS R1,R2
346
347 /* Check the parameters */
348 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
349
350 tmpreg = RCC->CFGR;
\ 00000004 .... LDR.N R2,??DataTable38 ;; 0x40021004
\ 00000006 1268 LDR R2,[R2, #+0]
\ 00000008 1100 MOVS R1,R2
351
352 /* Clear SW[1:0] bits */
353 tmpreg &= CFGR_SW_Mask;
\ 0000000A 0322 MOVS R2,#+3
\ 0000000C 9143 BICS R1,R1,R2
354
355 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
356 tmpreg |= RCC_SYSCLKSource;
\ 0000000E 0143 ORRS R1,R1,R0
357
358 /* Store the new value */
359 RCC->CFGR = tmpreg;
\ 00000010 .... LDR.N R2,??DataTable38 ;; 0x40021004
\ 00000012 1160 STR R1,[R2, #+0]
360 }
\ 00000014 7047 BX LR ;; return
361
362 /*******************************************************************************
363 * Function Name : RCC_GetSYSCLKSource
364 * Description : Returns the clock source used as system clock.
365 * Input : None
366 * Output : None
367 * Return : The clock source used as system clock. The returned value can
368 * be one of the following:
369 * - 0x00: HSI used as system clock
370 * - 0x04: HSE used as system clock
371 * - 0x08: PLL used as system clock
372 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
373 u8 RCC_GetSYSCLKSource(void)
374 {
375 return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
\ RCC_GetSYSCLKSource:
\ 00000000 .... LDR.N R0,??DataTable38 ;; 0x40021004
\ 00000002 0068 LDR R0,[R0, #+0]
\ 00000004 10F00C00 ANDS R0,R0,#0xC
\ 00000008 7047 BX LR ;; return
376 }
377
378 /*******************************************************************************
379 * Function Name : RCC_HCLKConfig
380 * Description : Configures the AHB clock (HCLK).
381 * Input : - RCC_HCLK: defines the AHB clock. This clock is derived
382 * from the system clock (SYSCLK).
383 * This parameter can be one of the following values:
384 * - RCC_SYSCLK_Div1: AHB clock = SYSCLK
385 * - RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
386 * - RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
387 * - RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
388 * - RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
389 * - RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
390 * - RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
391 * - RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
392 * - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
393 * Output : None
394 * Return : None
395 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
396 void RCC_HCLKConfig(u32 RCC_HCLK)
397 {
398 u32 tmpreg = 0;
\ RCC_HCLKConfig:
\ 00000000 0022 MOVS R2,#+0
\ 00000002 1100 MOVS R1,R2
399
400 /* Check the parameters */
401 assert_param(IS_RCC_HCLK(RCC_HCLK));
402
403 tmpreg = RCC->CFGR;
\ 00000004 .... LDR.N R2,??DataTable38 ;; 0x40021004
\ 00000006 1268 LDR R2,[R2, #+0]
\ 00000008 1100 MOVS R1,R2
404
405 /* Clear HPRE[7:4] bits */
406 tmpreg &= CFGR_HPRE_Reset_Mask;
\ 0000000A F022 MOVS R2,#+240
\ 0000000C 9143 BICS R1,R1,R2
407
408 /* Set HPRE[7:4] bits according to RCC_HCLK value */
409 tmpreg |= RCC_HCLK;
\ 0000000E 0143 ORRS R1,R1,R0
410
411 /* Store the new value */
412 RCC->CFGR = tmpreg;
\ 00000010 .... LDR.N R2,??DataTable38 ;; 0x40021004
\ 00000012 1160 STR R1,[R2, #+0]
413 }
\ 00000014 7047 BX LR ;; return
414
415 /*******************************************************************************
416 * Function Name : RCC_PCLK1Config
417 * Description : Configures the Low Speed APB clock (PCLK1).
418 * Input : - RCC_PCLK1: defines the APB1 clock. This clock is derived
419 * from the AHB clock (HCLK).
420 * This parameter can be one of the following values:
421 * - RCC_HCLK_Div1: APB1 clock = HCLK
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