📄 stm32f10x_rcc.lst
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# #
# 30/Jul/2008 14:37:36 #
# IAR ARM ANSI C/C++ Compiler V5.11.0.20622/W32 EVALUATION #
# Copyright 1999-2007 IAR Systems. All rights reserved. #
# #
# Cpu mode = thumb #
# Endian = little #
# Source file = E:\library\src\stm32f10x_rcc.c #
# Command line = E:\library\src\stm32f10x_rcc.c -D EMB_FLASH -lCN #
# E:\ELE\yten\pro\Debug\List\ -lb #
# E:\ELE\yten\pro\Debug\List\ -o #
# E:\ELE\yten\pro\Debug\Obj\ --no_cse --no_unroll #
# --no_inline --no_code_motion --no_tbaa --no_clustering #
# --no_scheduling --debug --endian little --cpu Cortex-M3 #
# -e --fpu None --dlib_config "C:\Program Files\IAR #
# Systems\Embedded Workbench 5.0 #
# Evaluation\ARM\INC\DLib_Config_Normal.h" -I #
# E:\ELE\yten\pro\ -I E:\ELE\yten\pro\..\LIBRARY\INC\ -I #
# "C:\Program Files\IAR Systems\Embedded Workbench 5.0 #
# Evaluation\ARM\INC\" --section .text=.XML -On #
# List file = E:\ELE\yten\pro\Debug\List\stm32f10x_rcc.lst #
# Object file = E:\ELE\yten\pro\Debug\Obj\stm32f10x_rcc.o #
# #
# #
###############################################################################
E:\library\src\stm32f10x_rcc.c
1 /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
2 * File Name : stm32f10x_rcc.c
3 * Author : MCD Application Team
4 * Version : V1.0
5 * Date : 10/08/2007
6 * Description : This file provides all the RCC firmware functions.
7 ********************************************************************************
8 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
9 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
10 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
11 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
12 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
13 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
14 *******************************************************************************/
15
16 /* Includes ------------------------------------------------------------------*/
17 #include "stm32f10x_rcc.h"
18
19 /* Private typedef -----------------------------------------------------------*/
20 /* Private define ------------------------------------------------------------*/
21 /* ------------ RCC registers bit address in the alias region ----------- */
22 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
23
24 /* --- CR Register ---*/
25 /* Alias word address of HSION bit */
26 #define CR_OFFSET (RCC_OFFSET + 0x00)
27 #define HSION_BitNumber 0x00
28 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
29
30 /* Alias word address of PLLON bit */
31 #define PLLON_BitNumber 0x18
32 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
33
34 /* Alias word address of CSSON bit */
35 #define CSSON_BitNumber 0x13
36 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
37
38 /* --- CFGR Register ---*/
39 /* Alias word address of USBPRE bit */
40 #define CFGR_OFFSET (RCC_OFFSET + 0x04)
41 #define USBPRE_BitNumber 0x16
42 #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
43
44 /* --- BDCR Register ---*/
45 /* Alias word address of RTCEN bit */
46 #define BDCR_OFFSET (RCC_OFFSET + 0x20)
47 #define RTCEN_BitNumber 0x0F
48 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
49
50 /* Alias word address of BDRST bit */
51 #define BDRST_BitNumber 0x10
52 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
53
54 /* --- CSR Register ---*/
55 /* Alias word address of LSION bit */
56 #define CSR_OFFSET (RCC_OFFSET + 0x24)
57 #define LSION_BitNumber 0x00
58 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
59
60 /* ---------------------- RCC registers bit mask ------------------------ */
61 /* CR register bit mask */
62 #define CR_HSEBYP_Reset ((u32)0xFFFBFFFF)
63 #define CR_HSEBYP_Set ((u32)0x00040000)
64 #define CR_HSEON_Reset ((u32)0xFFFEFFFF)
65 #define CR_HSEON_Set ((u32)0x00010000)
66 #define CR_HSITRIM_Mask ((u32)0xFFFFFF07)
67
68 /* CFGR register bit mask */
69 #define CFGR_PLL_Mask ((u32)0xFFC0FFFF)
70 #define CFGR_PLLMull_Mask ((u32)0x003C0000)
71 #define CFGR_PLLSRC_Mask ((u32)0x00010000)
72 #define CFGR_PLLXTPRE_Mask ((u32)0x00020000)
73 #define CFGR_SWS_Mask ((u32)0x0000000C)
74 #define CFGR_SW_Mask ((u32)0xFFFFFFFC)
75 #define CFGR_HPRE_Reset_Mask ((u32)0xFFFFFF0F)
76 #define CFGR_HPRE_Set_Mask ((u32)0x000000F0)
77 #define CFGR_PPRE1_Reset_Mask ((u32)0xFFFFF8FF)
78 #define CFGR_PPRE1_Set_Mask ((u32)0x00000700)
79 #define CFGR_PPRE2_Reset_Mask ((u32)0xFFFFC7FF)
80 #define CFGR_PPRE2_Set_Mask ((u32)0x00003800)
81 #define CFGR_ADCPRE_Reset_Mask ((u32)0xFFFF3FFF)
82 #define CFGR_ADCPRE_Set_Mask ((u32)0x0000C000)
83
84 /* CSR register bit mask */
85 #define CSR_RMVF_Set ((u32)0x01000000)
86
87 /* RCC Flag Mask */
88 #define FLAG_Mask ((u8)0x1F)
89
90 /* Typical Value of the HSI in Hz */
91 #define HSI_Value ((u32)8000000)
92
93 /* BDCR register base address */
94 #define BDCR_BASE (PERIPH_BASE + BDCR_OFFSET)
95
96 /* Time out for HSE start up */
97 #define HSEStartUp_TimeOut ((u8)0xFF)
98
99 /* Private macro -------------------------------------------------------------*/
100 /* Private variables ---------------------------------------------------------*/
\ In section .rodata, align 4
101 static uc8 APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
\ APBAHBPrescTable:
\ 00000000 000000000102 DC8 0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9
\ 030401020304
\ 06070809
\ In section .rodata, align 4
102 static uc8 ADCPrescTable[4] = {2, 4, 6, 8};
\ ADCPrescTable:
\ 00000000 02040608 DC8 2, 4, 6, 8
103
\ In section .bss, align 1
104 static volatile FlagStatus HSEStatus;
\ HSEStatus:
\ 00000000 DS8 1
\ In section .bss, align 4
105 static vu32 StartUpCounter = 0;
\ StartUpCounter:
\ 00000000 DS8 4
106
107 /* Private function prototypes -----------------------------------------------*/
108 /* Private functions ---------------------------------------------------------*/
109
110 /*******************************************************************************
111 * Function Name : RCC_DeInit
112 * Description : Deinitializes the RCC peripheral registers to their default
113 * reset values.
114 * - The HSITRIM[4:0] bits in RCC_CR register are not modified
115 * by this function.
116 * - The RCC_BDCR and RCC_CSR registers are not reset by this
117 * function.
118 * Input : None
119 * Output : None
120 * Return : None
121 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
122 void RCC_DeInit(void)
123 {
124 /* Disable APB2 Peripheral Reset */
125 RCC->APB2RSTR = 0x00000000;
\ RCC_DeInit:
\ 00000000 .... LDR.N R0,??DataTable0 ;; 0x4002100c
\ 00000002 0021 MOVS R1,#+0
\ 00000004 0160 STR R1,[R0, #+0]
126
127 /* Disable APB1 Peripheral Reset */
128 RCC->APB1RSTR = 0x00000000;
\ 00000006 .... LDR.N R0,??DataTable1 ;; 0x40021010
\ 00000008 0021 MOVS R1,#+0
\ 0000000A 0160 STR R1,[R0, #+0]
129
130 /* FLITF and SRAM Clock ON */
131 RCC->AHBENR = 0x00000014;
\ 0000000C .... LDR.N R0,??DataTable2 ;; 0x40021014
\ 0000000E 1421 MOVS R1,#+20
\ 00000010 0160 STR R1,[R0, #+0]
132
133 /* Disable APB2 Peripheral Clock */
134 RCC->APB2ENR = 0x00000000;
\ 00000012 .... LDR.N R0,??DataTable3 ;; 0x40021018
\ 00000014 0021 MOVS R1,#+0
\ 00000016 0160 STR R1,[R0, #+0]
135
136 /* Disable APB1 Peripheral Clock */
137 RCC->APB1ENR = 0x00000000;
\ 00000018 .... LDR.N R0,??DataTable4 ;; 0x4002101c
\ 0000001A 0021 MOVS R1,#+0
\ 0000001C 0160 STR R1,[R0, #+0]
138
139 /* Set HSION bit */
140 RCC->CR |= (u32)0x00000001;
\ 0000001E .... LDR.N R0,??DataTable25 ;; 0x40021000
\ 00000020 0068 LDR R0,[R0, #+0]
\ 00000022 50F00100 ORRS R0,R0,#0x1
\ 00000026 .... LDR.N R1,??DataTable25 ;; 0x40021000
\ 00000028 0860 STR R0,[R1, #+0]
141
142 /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits*/
143 RCC->CFGR &= 0xF8FF0000;
\ 0000002A .... LDR.N R0,??DataTable38 ;; 0x40021004
\ 0000002C 0068 LDR R0,[R0, #+0]
\ 0000002E 0E49 LDR.N R1,??RCC_DeInit_0 ;; 0xf8ff0000
\ 00000030 0140 ANDS R1,R1,R0
\ 00000032 .... LDR.N R0,??DataTable38 ;; 0x40021004
\ 00000034 0160 STR R1,[R0, #+0]
144
145 /* Reset HSEON, CSSON and PLLON bits */
146 RCC->CR &= 0xFEF6FFFF;
\ 00000036 .... LDR.N R0,??DataTable25 ;; 0x40021000
\ 00000038 0068 LDR R0,[R0, #+0]
\ 0000003A 0C49 LDR.N R1,??RCC_DeInit_0+0x4 ;; 0xfef6ffff
\ 0000003C 0140 ANDS R1,R1,R0
\ 0000003E .... LDR.N R0,??DataTable25 ;; 0x40021000
\ 00000040 0160 STR R1,[R0, #+0]
147
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