📄 stm32f10x_tim1.lst
字号:
\ 0000002C .... LDR.N R3,??DataTable27 ;; 0x42258424
\ 0000002E 1A60 STR R2,[R3, #+0]
483
484 /* Set the Output N Polarity */
485 *(vu32 *) CCER_CC3NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
\ 00000030 4289 LDRH R2,[R0, #+10]
\ 00000032 .... LDR.N R3,??DataTable28 ;; 0x4225842c
\ 00000034 1A60 STR R2,[R3, #+0]
486
487 /* Set the Output Idle state */
488 *(vu32 *) CR2_OIS3_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
\ 00000036 8289 LDRH R2,[R0, #+12]
\ 00000038 044B LDR.N R3,??TIM1_OC3Init_0 ;; 0x422580b0
\ 0000003A 1A60 STR R2,[R3, #+0]
489
490 /* Set the Output N Idle state */
491 *(vu32 *) CR2_OIS3N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
\ 0000003C C289 LDRH R2,[R0, #+14]
\ 0000003E 044B LDR.N R3,??TIM1_OC3Init_0+0x4 ;; 0x422580b4
\ 00000040 1A60 STR R2,[R3, #+0]
492
493 /* Set the Pulse value */
494 TIM1->CCR3 = TIM1_OCInitStruct->TIM1_Pulse;
\ 00000042 C288 LDRH R2,[R0, #+6]
\ 00000044 .... LDR.N R3,??DataTable29 ;; 0x40012c3c
\ 00000046 1A80 STRH R2,[R3, #+0]
495 }
\ 00000048 7047 BX LR ;; return
\ 0000004A 00BF Nop
\ ??TIM1_OC3Init_0:
\ 0000004C B0802542 DC32 0x422580b0
\ 00000050 B4802542 DC32 0x422580b4
496
497 /*******************************************************************************
498 * Function Name : TIM1_OC4Init
499 * Description : Initializes the TIM1 Channel4 according to the specified
500 * parameters in the TIM1_OCInitStruct.
501 * Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
502 * contains the configuration information for the TIM1 peripheral.
503 * Output : None
504 * Return : None
505 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
506 void TIM1_OC4Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
507 {
508 u32 tmpccmr = 0;
\ TIM1_OC4Init:
\ 00000000 0022 MOVS R2,#+0
\ 00000002 1100 MOVS R1,R2
509
510 /* Check the parameters */
511 assert_param(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
512 assert_param(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
513 assert_param(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
514 assert_param(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
515
516 tmpccmr = TIM1->CCMR2;
\ 00000004 .... LDR.N R2,??DataTable32 ;; 0x40012c1c
\ 00000006 1288 LDRH R2,[R2, #+0]
\ 00000008 92B2 UXTH R2,R2 ;; ZeroExtS R2,R2,#+16,#+16
\ 0000000A 1100 MOVS R1,R2
517
518 /* Disable the Channel 4: Reset the CCE Bit */
519 *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset;
\ 0000000C .... LDR.N R2,??DataTable33 ;; 0x42258430
\ 0000000E 0023 MOVS R3,#+0
\ 00000010 1360 STR R3,[R2, #+0]
520
521 /* Reset the Output Compare Bits */
522 tmpccmr &= OC24Mode_Mask;
\ 00000012 C9B2 UXTB R1,R1 ;; ZeroExtS R1,R1,#+24,#+24
523
524 /* Set the Ouput Compare Mode */
525 tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8;
\ 00000014 0288 LDRH R2,[R0, #+0]
\ 00000016 51EA0221 ORRS R1,R1,R2, LSL #+8
526
527 TIM1->CCMR2 = (u16)tmpccmr;
\ 0000001A .... LDR.N R2,??DataTable32 ;; 0x40012c1c
\ 0000001C 0B00 MOVS R3,R1
\ 0000001E 1380 STRH R3,[R2, #+0]
528
529 /* Set the Output State */
530 *(vu32 *) CCER_CC4E_BB = TIM1_OCInitStruct->TIM1_OutputState;
\ 00000020 4288 LDRH R2,[R0, #+2]
\ 00000022 .... LDR.N R3,??DataTable33 ;; 0x42258430
\ 00000024 1A60 STR R2,[R3, #+0]
531
532 /* Set the Output Polarity */
533 *(vu32 *) CCER_CC4P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
\ 00000026 0289 LDRH R2,[R0, #+8]
\ 00000028 .... LDR.N R3,??DataTable34 ;; 0x42258434
\ 0000002A 1A60 STR R2,[R3, #+0]
534
535 /* Set the Output Idle state */
536 *(vu32 *) CR2_OIS4_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
\ 0000002C 8289 LDRH R2,[R0, #+12]
\ 0000002E 034B LDR.N R3,??TIM1_OC4Init_0 ;; 0x422580b8
\ 00000030 1A60 STR R2,[R3, #+0]
537
538 /* Set the Pulse value */
539 TIM1->CCR4 = TIM1_OCInitStruct->TIM1_Pulse;
\ 00000032 C288 LDRH R2,[R0, #+6]
\ 00000034 .... LDR.N R3,??DataTable35 ;; 0x40012c40
\ 00000036 1A80 STRH R2,[R3, #+0]
540 }
\ 00000038 7047 BX LR ;; return
\ 0000003A 00BF Nop
\ ??TIM1_OC4Init_0:
\ 0000003C B8802542 DC32 0x422580b8
541
542 /*******************************************************************************
543 * Function Name : TIM1_BDTRConfig
544 * Description : Configures the: Break feature, dead time, Lock level, the OSSI,
545 * the OSSR State and the AOE(automatic output enable).
546 * Input : - TIM1_BDTRInitStruct: pointer to a TIM1_BDTRInitTypeDef
547 * structure that contains the BDTR Register configuration
548 * information for the TIM1 peripheral.
549 * Output : None
550 * Return : None
551 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
552 void TIM1_BDTRConfig(TIM1_BDTRInitTypeDef *TIM1_BDTRInitStruct)
553 {
554 u16 tmpbdtr = 0;
\ TIM1_BDTRConfig:
\ 00000000 0022 MOVS R2,#+0
\ 00000002 1100 MOVS R1,R2
555
556 /* Check the parameters */
557 assert_param(IS_TIM1_OSSR_STATE(TIM1_BDTRInitStruct->TIM1_OSSRState));
558 assert_param(IS_TIM1_OSSI_STATE(TIM1_BDTRInitStruct->TIM1_OSSIState));
559 assert_param(IS_TIM1_LOCK_LEVEL(TIM1_BDTRInitStruct->TIM1_LOCKLevel));
560 assert_param(IS_TIM1_BREAK_STATE(TIM1_BDTRInitStruct->TIM1_Break));
561 assert_param(IS_TIM1_BREAK_POLARITY(TIM1_BDTRInitStruct->TIM1_BreakPolarity));
562 assert_param(IS_TIM1_AUTOMATIC_OUTPUT_STATE(TIM1_BDTRInitStruct->TIM1_AutomaticOutput));
563
564 tmpbdtr = TIM1->BDTR;
\ 00000004 094A LDR.N R2,??TIM1_BDTRConfig_0 ;; 0x40012c44
\ 00000006 1288 LDRH R2,[R2, #+0]
\ 00000008 1100 MOVS R1,R2
565
566 /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
567 the OSSI State, the dead time value and the Automatic Output Enable Bit */
568
569 tmpbdtr = (u32)TIM1_BDTRInitStruct->TIM1_OSSRState | TIM1_BDTRInitStruct->TIM1_OSSIState |
570 TIM1_BDTRInitStruct->TIM1_LOCKLevel | TIM1_BDTRInitStruct->TIM1_DeadTime |
571 TIM1_BDTRInitStruct->TIM1_Break | TIM1_BDTRInitStruct->TIM1_BreakPolarity |
572 TIM1_BDTRInitStruct->TIM1_AutomaticOutput;
\ 0000000A 0288 LDRH R2,[R0, #+0]
\ 0000000C 4388 LDRH R3,[R0, #+2]
\ 0000000E 1343 ORRS R3,R3,R2
\ 00000010 8288 LDRH R2,[R0, #+4]
\ 00000012 1A43 ORRS R2,R2,R3
\ 00000014 C388 LDRH R3,[R0, #+6]
\ 00000016 1343 ORRS R3,R3,R2
\ 00000018 0289 LDRH R2,[R0, #+8]
\ 0000001A 1A43 ORRS R2,R2,R3
\ 0000001C 4389 LDRH R3,[R0, #+10]
\ 0000001E 1343 ORRS R3,R3,R2
\ 00000020 8289 LDRH R2,[R0, #+12]
\ 00000022 1A43 ORRS R2,R2,R3
\ 00000024 1100 MOVS R1,R2
573
574 TIM1->BDTR = tmpbdtr;
\ 00000026 014A LDR.N R2,??TIM1_BDTRConfig_0 ;; 0x40012c44
\ 00000028 1180 STRH R1,[R2, #+0]
575 }
\ 0000002A 7047 BX LR ;; return
\ ??TIM1_BDTRConfig_0:
\ 0000002C 442C0140 DC32 0x40012c44
576
577 /*******************************************************************************
578 * Function Name : TIM1_ICInit
579 * Description : Initializes the TIM1 peripheral according to the specified
580 * parameters in the TIM1_ICInitStruct.
581 * Input : - TIM1_ICInitStruct: pointer to a TIM1_ICInitTypeDef structure
582 * that contains the configuration information for the specified
583 * TIM1 peripheral.
584 * Output : None
585 * Return : None
586 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
587 void TIM1_ICInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct)
588 {
\ TIM1_ICInit:
\ 00000000 10B5 PUSH {R4,LR}
\ 00000002 0400 MOVS R4,R0
589 /* Check the parameters */
590 assert_param(IS_TIM1_CHANNEL(TIM1_ICInitStruct->TIM1_Channel));
591 assert_param(IS_TIM1_IC_POLARITY(TIM1_ICInitStruct->TIM1_ICPolarity));
592 assert_param(IS_TIM1_IC_SELECTION(TIM1_ICInitStruct->TIM1_ICSelection));
593 assert_param(IS_TIM1_IC_PRESCALER(TIM1_ICInitStruct->TIM1_ICPrescaler));
594 assert_param(IS_TIM1_IC_FILTER(TIM1_ICInitStruct->TIM1_ICFilter));
595
596 if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_1)
\ 00000004 2088 LDRH R0,[R4, #+0]
\ 00000006 0028 CMP R0,#+0
\ 00000008 08D1 BNE.N ??TIM1_ICInit_0
597 {
598 /* TI1 Configuration */
599 TI1_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
600 TIM1_ICInitStruct->TIM1_ICSelection,
601 TIM1_ICInitStruct->TIM1_ICFilter);
\ 0000000A 227A LDRB R2,[R4, #+8]
\ 0000000C A188 LDRH R1,[R4, #+4]
\ 0000000E 6088 LDRH R0,[R4, #+2]
\ 00000010 ........ BL TI1_Config
602
603 /* Set the Input Capture Prescaler value */
604 TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
\ 00000014 E088 LDRH R0,[R4, #+6]
\ 00000016 ........ BL TIM1_SetIC1Prescaler
\ 0000001A 1FE0 B.N ??TIM1_ICInit_1
605 }
606 else if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_2)
\ ??TIM1_ICInit_0:
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -