📄 stm32f10x_tim1.lst
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358
359 TIM1->CCMR1 = tmpccmr;
\ 0000001A .... LDR.N R2,??DataTable16 ;; 0x40012c18
\ 0000001C 1180 STRH R1,[R2, #+0]
360
361 /* Set the Output State */
362 *(vu32 *) CCER_CC1E_BB = TIM1_OCInitStruct->TIM1_OutputState;
\ 0000001E 4288 LDRH R2,[R0, #+2]
\ 00000020 .... LDR.N R3,??DataTable9 ;; 0x42258400
\ 00000022 1A60 STR R2,[R3, #+0]
363
364 /* Set the Output N State */
365 *(vu32 *) CCER_CC1NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
\ 00000024 8288 LDRH R2,[R0, #+4]
\ 00000026 .... LDR.N R3,??DataTable10 ;; 0x42258408
\ 00000028 1A60 STR R2,[R3, #+0]
366
367 /* Set the Output Polarity */
368 *(vu32 *) CCER_CC1P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
\ 0000002A 0289 LDRH R2,[R0, #+8]
\ 0000002C .... LDR.N R3,??DataTable11 ;; 0x42258404
\ 0000002E 1A60 STR R2,[R3, #+0]
369
370 /* Set the Output N Polarity */
371 *(vu32 *) CCER_CC1NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
\ 00000030 4289 LDRH R2,[R0, #+10]
\ 00000032 .... LDR.N R3,??DataTable12 ;; 0x4225840c
\ 00000034 1A60 STR R2,[R3, #+0]
372
373 /* Set the Output Idle state */
374 *(vu32 *) CR2_OIS1_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
\ 00000036 8289 LDRH R2,[R0, #+12]
\ 00000038 044B LDR.N R3,??TIM1_OC1Init_0 ;; 0x422580a0
\ 0000003A 1A60 STR R2,[R3, #+0]
375
376 /* Set the Output N Idle state */
377 *(vu32 *) CR2_OIS1N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
\ 0000003C C289 LDRH R2,[R0, #+14]
\ 0000003E 044B LDR.N R3,??TIM1_OC1Init_0+0x4 ;; 0x422580a4
\ 00000040 1A60 STR R2,[R3, #+0]
378
379 /* Set the Pulse value */
380 TIM1->CCR1 = TIM1_OCInitStruct->TIM1_Pulse;
\ 00000042 C288 LDRH R2,[R0, #+6]
\ 00000044 .... LDR.N R3,??DataTable13 ;; 0x40012c34
\ 00000046 1A80 STRH R2,[R3, #+0]
381 }
\ 00000048 7047 BX LR ;; return
\ 0000004A 00BF Nop
\ ??TIM1_OC1Init_0:
\ 0000004C A0802542 DC32 0x422580a0
\ 00000050 A4802542 DC32 0x422580a4
382
383 /*******************************************************************************
384 * Function Name : TIM1_OC2Init
385 * Description : Initializes the TIM1 Channel2 according to the specified
386 * parameters in the TIM1_OCInitStruct.
387 * Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
388 * contains the configuration information for the TIM1 peripheral.
389 * Output : None
390 * Return : None
391 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
392 void TIM1_OC2Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
393 {
394 u32 tmpccmr = 0;
\ TIM1_OC2Init:
\ 00000000 0022 MOVS R2,#+0
\ 00000002 1100 MOVS R1,R2
395
396 /* Check the parameters */
397 assert_param(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
398 assert_param(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
399 assert_param(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));
400 assert_param(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
401 assert_param(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
402 assert_param(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
403 assert_param(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));
404
405 tmpccmr = TIM1->CCMR1;
\ 00000004 .... LDR.N R2,??DataTable16 ;; 0x40012c18
\ 00000006 1288 LDRH R2,[R2, #+0]
\ 00000008 92B2 UXTH R2,R2 ;; ZeroExtS R2,R2,#+16,#+16
\ 0000000A 1100 MOVS R1,R2
406
407 /* Disable the Channel 2: Reset the CCE Bit */
408 *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset;
\ 0000000C .... LDR.N R2,??DataTable17 ;; 0x42258410
\ 0000000E 0023 MOVS R3,#+0
\ 00000010 1360 STR R3,[R2, #+0]
409
410 /* Reset the Output Compare Bits */
411 tmpccmr &= OC24Mode_Mask;
\ 00000012 C9B2 UXTB R1,R1 ;; ZeroExtS R1,R1,#+24,#+24
412
413 /* Set the Ouput Compare Mode */
414 tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8;
\ 00000014 0288 LDRH R2,[R0, #+0]
\ 00000016 51EA0221 ORRS R1,R1,R2, LSL #+8
415
416 TIM1->CCMR1 = (u16)tmpccmr;
\ 0000001A .... LDR.N R2,??DataTable16 ;; 0x40012c18
\ 0000001C 0B00 MOVS R3,R1
\ 0000001E 1380 STRH R3,[R2, #+0]
417
418 /* Set the Output State */
419 *(vu32 *) CCER_CC2E_BB = TIM1_OCInitStruct->TIM1_OutputState;
\ 00000020 4288 LDRH R2,[R0, #+2]
\ 00000022 .... LDR.N R3,??DataTable17 ;; 0x42258410
\ 00000024 1A60 STR R2,[R3, #+0]
420
421 /* Set the Output N State */
422 *(vu32 *) CCER_CC2NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
\ 00000026 8288 LDRH R2,[R0, #+4]
\ 00000028 .... LDR.N R3,??DataTable18 ;; 0x42258418
\ 0000002A 1A60 STR R2,[R3, #+0]
423
424 /* Set the Output Polarity */
425 *(vu32 *) CCER_CC2P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
\ 0000002C 0289 LDRH R2,[R0, #+8]
\ 0000002E .... LDR.N R3,??DataTable19 ;; 0x42258414
\ 00000030 1A60 STR R2,[R3, #+0]
426
427 /* Set the Output N Polarity */
428 *(vu32 *) CCER_CC2NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
\ 00000032 4289 LDRH R2,[R0, #+10]
\ 00000034 .... LDR.N R3,??DataTable20 ;; 0x4225841c
\ 00000036 1A60 STR R2,[R3, #+0]
429
430 /* Set the Output Idle state */
431 *(vu32 *) CR2_OIS2_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
\ 00000038 8289 LDRH R2,[R0, #+12]
\ 0000003A 044B LDR.N R3,??TIM1_OC2Init_0 ;; 0x422580a8
\ 0000003C 1A60 STR R2,[R3, #+0]
432
433 /* Set the Output N Idle state */
434 *(vu32 *) CR2_OIS2N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
\ 0000003E C289 LDRH R2,[R0, #+14]
\ 00000040 034B LDR.N R3,??TIM1_OC2Init_0+0x4 ;; 0x422580ac
\ 00000042 1A60 STR R2,[R3, #+0]
435
436 /* Set the Pulse value */
437 TIM1->CCR2 = TIM1_OCInitStruct->TIM1_Pulse;
\ 00000044 C288 LDRH R2,[R0, #+6]
\ 00000046 .... LDR.N R3,??DataTable21 ;; 0x40012c38
\ 00000048 1A80 STRH R2,[R3, #+0]
438 }
\ 0000004A 7047 BX LR ;; return
\ ??TIM1_OC2Init_0:
\ 0000004C A8802542 DC32 0x422580a8
\ 00000050 AC802542 DC32 0x422580ac
439
440 /*******************************************************************************
441 * Function Name : TIM1_OC3Init
442 * Description : Initializes the TIM1 Channel3 according to the specified
443 * parameters in the TIM1_OCInitStruct.
444 * Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
445 * contains the configuration information for the TIM1 peripheral.
446 * Output : None
447 * Return : None
448 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
449 void TIM1_OC3Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
450 {
451 u16 tmpccmr = 0;
\ TIM1_OC3Init:
\ 00000000 0022 MOVS R2,#+0
\ 00000002 1100 MOVS R1,R2
452
453 /* Check the parameters */
454 assert_param(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
455 assert_param(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
456 assert_param(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));
457 assert_param(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
458 assert_param(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
459 assert_param(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
460 assert_param(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));
461
462 tmpccmr = TIM1->CCMR2;
\ 00000004 .... LDR.N R2,??DataTable32 ;; 0x40012c1c
\ 00000006 1288 LDRH R2,[R2, #+0]
\ 00000008 1100 MOVS R1,R2
463
464 /* Disable the Channel 3: Reset the CCE Bit */
465 *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset;
\ 0000000A .... LDR.N R2,??DataTable25 ;; 0x42258420
\ 0000000C 0023 MOVS R3,#+0
\ 0000000E 1360 STR R3,[R2, #+0]
466
467 /* Reset the Output Compare Bits */
468 tmpccmr &= OC13Mode_Mask;
\ 00000010 11F47F41 ANDS R1,R1,#0xFF00
469
470 /* Set the Ouput Compare Mode */
471 tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode;
\ 00000014 0A00 MOVS R2,R1
\ 00000016 0188 LDRH R1,[R0, #+0]
\ 00000018 1143 ORRS R1,R1,R2
472
473 TIM1->CCMR2 = tmpccmr;
\ 0000001A .... LDR.N R2,??DataTable32 ;; 0x40012c1c
\ 0000001C 1180 STRH R1,[R2, #+0]
474
475 /* Set the Output State */
476 *(vu32 *) CCER_CC3E_BB = TIM1_OCInitStruct->TIM1_OutputState;
\ 0000001E 4288 LDRH R2,[R0, #+2]
\ 00000020 .... LDR.N R3,??DataTable25 ;; 0x42258420
\ 00000022 1A60 STR R2,[R3, #+0]
477
478 /* Set the Output N State */
479 *(vu32 *) CCER_CC3NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
\ 00000024 8288 LDRH R2,[R0, #+4]
\ 00000026 .... LDR.N R3,??DataTable26 ;; 0x42258428
\ 00000028 1A60 STR R2,[R3, #+0]
480
481 /* Set the Output Polarity */
482 *(vu32 *) CCER_CC3P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
\ 0000002A 0289 LDRH R2,[R0, #+8]
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