📄 stm32f10x_dma.lst
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###############################################################################
# #
# 30/Jul/2008 14:37:39 #
# IAR ARM ANSI C/C++ Compiler V5.11.0.20622/W32 EVALUATION #
# Copyright 1999-2007 IAR Systems. All rights reserved. #
# #
# Cpu mode = thumb #
# Endian = little #
# Source file = E:\library\src\stm32f10x_dma.c #
# Command line = E:\library\src\stm32f10x_dma.c -D EMB_FLASH -lCN #
# E:\ELE\yten\pro\Debug\List\ -lb #
# E:\ELE\yten\pro\Debug\List\ -o #
# E:\ELE\yten\pro\Debug\Obj\ --no_cse --no_unroll #
# --no_inline --no_code_motion --no_tbaa --no_clustering #
# --no_scheduling --debug --endian little --cpu Cortex-M3 #
# -e --fpu None --dlib_config "C:\Program Files\IAR #
# Systems\Embedded Workbench 5.0 #
# Evaluation\ARM\INC\DLib_Config_Normal.h" -I #
# E:\ELE\yten\pro\ -I E:\ELE\yten\pro\..\LIBRARY\INC\ -I #
# "C:\Program Files\IAR Systems\Embedded Workbench 5.0 #
# Evaluation\ARM\INC\" --section .text=.XML -On #
# List file = E:\ELE\yten\pro\Debug\List\stm32f10x_dma.lst #
# Object file = E:\ELE\yten\pro\Debug\Obj\stm32f10x_dma.o #
# #
# #
###############################################################################
E:\library\src\stm32f10x_dma.c
1 /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
2 * File Name : stm32f10x_dma.c
3 * Author : MCD Application Team
4 * Version : V1.0
5 * Date : 10/08/2007
6 * Description : This file provides all the DMA firmware functions.
7 ********************************************************************************
8 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
9 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
10 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
11 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
12 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
13 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
14 *******************************************************************************/
15
16 /* Includes ------------------------------------------------------------------*/
17 #include "stm32f10x_dma.h"
18 #include "stm32f10x_rcc.h"
19
20 /* Private typedef -----------------------------------------------------------*/
21 /* Private define ------------------------------------------------------------*/
22 /* DMA ENABLE mask */
23 #define CCR_ENABLE_Set ((u32)0x00000001)
24 #define CCR_ENABLE_Reset ((u32)0xFFFFFFFE)
25
26 /* DMA Channelx interrupt pending bit masks */
27 #define DMA_Channel1_IT_Mask ((u32)0x0000000F)
28 #define DMA_Channel2_IT_Mask ((u32)0x000000F0)
29 #define DMA_Channel3_IT_Mask ((u32)0x00000F00)
30 #define DMA_Channel4_IT_Mask ((u32)0x0000F000)
31 #define DMA_Channel5_IT_Mask ((u32)0x000F0000)
32 #define DMA_Channel6_IT_Mask ((u32)0x00F00000)
33 #define DMA_Channel7_IT_Mask ((u32)0x0F000000)
34
35 /* DMA registers Masks */
36 #define CCR_CLEAR_Mask ((u32)0xFFFF800F)
37
38 /* Private macro -------------------------------------------------------------*/
39 /* Private variables ---------------------------------------------------------*/
40 /* Private function prototypes -----------------------------------------------*/
41 /* Private functions ---------------------------------------------------------*/
42
43 /*******************************************************************************
44 * Function Name : DMA_DeInit
45 * Description : Deinitializes the DMA Channelx registers to their default reset
46 * values.
47 * Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
48 * Channel.
49 * Output : None
50 * Return : None
51 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
52 void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx)
53 {
\ DMA_DeInit:
\ 00000000 10B5 PUSH {R4,LR}
\ 00000002 0400 MOVS R4,R0
54 /* DMA Channelx disable */
55 DMA_Cmd(DMA_Channelx, DISABLE);
\ 00000004 0021 MOVS R1,#+0
\ 00000006 2000 MOVS R0,R4
\ 00000008 ........ BL DMA_Cmd
56
57 /* Reset Channelx control register */
58 DMA_Channelx->CCR = 0;
\ 0000000C 0020 MOVS R0,#+0
\ 0000000E 2060 STR R0,[R4, #+0]
59
60 /* Reset Channelx remaining bytes register */
61 DMA_Channelx->CNDTR = 0;
\ 00000010 0020 MOVS R0,#+0
\ 00000012 6060 STR R0,[R4, #+4]
62
63 /* Reset Channelx peripheral address register */
64 DMA_Channelx->CPAR = 0;
\ 00000014 0020 MOVS R0,#+0
\ 00000016 A060 STR R0,[R4, #+8]
65
66 /* Reset Channelx memory address register */
67 DMA_Channelx->CMAR = 0;
\ 00000018 0020 MOVS R0,#+0
\ 0000001A E060 STR R0,[R4, #+12]
68
69 switch (*(u32*)&DMA_Channelx)
\ 0000001C 2000 MOVS R0,R4
\ 0000001E 2049 LDR.N R1,??DMA_DeInit_0 ;; 0x40020008
\ 00000020 401A SUBS R0,R0,R1
\ 00000022 0CD0 BEQ.N ??DMA_DeInit_1
\ 00000024 1438 SUBS R0,R0,#+20
\ 00000026 11D0 BEQ.N ??DMA_DeInit_2
\ 00000028 1438 SUBS R0,R0,#+20
\ 0000002A 16D0 BEQ.N ??DMA_DeInit_3
\ 0000002C 1438 SUBS R0,R0,#+20
\ 0000002E 1BD0 BEQ.N ??DMA_DeInit_4
\ 00000030 1438 SUBS R0,R0,#+20
\ 00000032 20D0 BEQ.N ??DMA_DeInit_5
\ 00000034 1438 SUBS R0,R0,#+20
\ 00000036 25D0 BEQ.N ??DMA_DeInit_6
\ 00000038 1438 SUBS R0,R0,#+20
\ 0000003A 2AD0 BEQ.N ??DMA_DeInit_7
\ 0000003C 2FE0 B.N ??DMA_DeInit_8
70 {
71 case DMA_Channel1_BASE:
72 /* Reset interrupt pending bits for Channel1 */
73 DMA->IFCR |= DMA_Channel1_IT_Mask;
\ ??DMA_DeInit_1:
\ 0000003E .... LDR.N R0,??DataTable17 ;; 0x40020004
\ 00000040 0068 LDR R0,[R0, #+0]
\ 00000042 50F00F00 ORRS R0,R0,#0xF
\ 00000046 .... LDR.N R1,??DataTable17 ;; 0x40020004
\ 00000048 0860 STR R0,[R1, #+0]
\ 0000004A 28E0 B.N ??DMA_DeInit_8
74 break;
75
76 case DMA_Channel2_BASE:
77 /* Reset interrupt pending bits for Channel2 */
78 DMA->IFCR |= DMA_Channel2_IT_Mask;
\ ??DMA_DeInit_2:
\ 0000004C .... LDR.N R0,??DataTable17 ;; 0x40020004
\ 0000004E 0068 LDR R0,[R0, #+0]
\ 00000050 50F0F000 ORRS R0,R0,#0xF0
\ 00000054 .... LDR.N R1,??DataTable17 ;; 0x40020004
\ 00000056 0860 STR R0,[R1, #+0]
\ 00000058 21E0 B.N ??DMA_DeInit_8
79 break;
80
81 case DMA_Channel3_BASE:
82 /* Reset interrupt pending bits for Channel3 */
83 DMA->IFCR |= DMA_Channel3_IT_Mask;
\ ??DMA_DeInit_3:
\ 0000005A .... LDR.N R0,??DataTable17 ;; 0x40020004
\ 0000005C 0068 LDR R0,[R0, #+0]
\ 0000005E 50F47060 ORRS R0,R0,#0xF00
\ 00000062 .... LDR.N R1,??DataTable17 ;; 0x40020004
\ 00000064 0860 STR R0,[R1, #+0]
\ 00000066 1AE0 B.N ??DMA_DeInit_8
84 break;
85
86 case DMA_Channel4_BASE:
87 /* Reset interrupt pending bits for Channel4 */
88 DMA->IFCR |= DMA_Channel4_IT_Mask;
\ ??DMA_DeInit_4:
\ 00000068 .... LDR.N R0,??DataTable17 ;; 0x40020004
\ 0000006A 0068 LDR R0,[R0, #+0]
\ 0000006C 50F47040 ORRS R0,R0,#0xF000
\ 00000070 .... LDR.N R1,??DataTable17 ;; 0x40020004
\ 00000072 0860 STR R0,[R1, #+0]
\ 00000074 13E0 B.N ??DMA_DeInit_8
89 break;
90
91 case DMA_Channel5_BASE:
92 /* Reset interrupt pending bits for Channel5 */
93 DMA->IFCR |= DMA_Channel5_IT_Mask;
\ ??DMA_DeInit_5:
\ 00000076 .... LDR.N R0,??DataTable17 ;; 0x40020004
\ 00000078 0068 LDR R0,[R0, #+0]
\ 0000007A 50F47020 ORRS R0,R0,#0xF0000
\ 0000007E .... LDR.N R1,??DataTable17 ;; 0x40020004
\ 00000080 0860 STR R0,[R1, #+0]
\ 00000082 0CE0 B.N ??DMA_DeInit_8
94 break;
95
96 case DMA_Channel6_BASE:
97 /* Reset interrupt pending bits for Channel6 */
98 DMA->IFCR |= DMA_Channel6_IT_Mask;
\ ??DMA_DeInit_6:
\ 00000084 .... LDR.N R0,??DataTable17 ;; 0x40020004
\ 00000086 0068 LDR R0,[R0, #+0]
\ 00000088 50F47000 ORRS R0,R0,#0xF00000
\ 0000008C .... LDR.N R1,??DataTable17 ;; 0x40020004
\ 0000008E 0860 STR R0,[R1, #+0]
\ 00000090 05E0 B.N ??DMA_DeInit_8
99 break;
100
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