📄 stm32f10x_tim.lst
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146 * Description : Initializes the TIMx Time Base Unit peripheral according to
147 * the specified parameters in the TIM_TimeBaseInitStruct.
148 * Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
149 * - TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
150 * structure that contains the configuration information for
151 * the specified TIM peripheral.
152 * Output : None
153 * Return : None
154 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
155 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
156 {
\ TIM_TimeBaseInit:
\ 00000000 11B4 PUSH {R0,R4}
157 /* Check the parameters */
158 assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
159 assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
160
161 /* Set the Autoreload value */
162 TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
\ 00000002 0A88 LDRH R2,[R1, #+0]
\ 00000004 8285 STRH R2,[R0, #+44]
163
164 /* Set the Prescaler value */
165 TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
\ 00000006 4A88 LDRH R2,[R1, #+2]
\ 00000008 0285 STRH R2,[R0, #+40]
166
167 /* Select the Counter Mode and set the clock division */
168 TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
\ 0000000A 0288 LDRH R2,[R0, #+0]
\ 0000000C 12F08F02 ANDS R2,R2,#0x8F
\ 00000010 0280 STRH R2,[R0, #+0]
169 TIMx->CR1 |= (u32)TIM_TimeBaseInitStruct->TIM_ClockDivision |
170 TIM_TimeBaseInitStruct->TIM_CounterMode;
\ 00000012 0288 LDRH R2,[R0, #+0]
\ 00000014 8B88 LDRH R3,[R1, #+4]
\ 00000016 CC88 LDRH R4,[R1, #+6]
\ 00000018 1C43 ORRS R4,R4,R3
\ 0000001A 1443 ORRS R4,R4,R2
\ 0000001C 0480 STRH R4,[R0, #+0]
171 }
\ 0000001E 01B0 ADD SP,SP,#+4
\ 00000020 10BC POP {R4}
\ 00000022 7047 BX LR ;; return
172 /*******************************************************************************
173 * Function Name : TIM_OCInit
174 * Description : Initializes the TIMx peripheral according to the specified
175 * parameters in the TIM_OCInitStruct.
176 * Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
177 * - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
178 * that contains the configuration information for the specified
179 * TIM peripheral.
180 * Output : None
181 * Return : None
182 *******************************************************************************/
\ In section .XML, align 4, keep-with-next
183 void TIM_OCInit(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
184 {
\ TIM_OCInit:
\ 00000000 30B4 PUSH {R4,R5}
185 u32 tmpccmrx = 0, tmpccer = 0;
\ 00000002 0024 MOVS R4,#+0
\ 00000004 2200 MOVS R2,R4
\ 00000006 0024 MOVS R4,#+0
\ 00000008 2300 MOVS R3,R4
186
187 /* Check the parameters */
188 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
189 assert_param(IS_TIM_CHANNEL(TIM_OCInitStruct->TIM_Channel));
190 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
191
192 tmpccer = TIMx->CCER;
\ 0000000A 048C LDRH R4,[R0, #+32]
\ 0000000C 2300 MOVS R3,R4
193
194 if ((TIM_OCInitStruct->TIM_Channel == (u16)TIM_Channel_1) ||
195 (TIM_OCInitStruct->TIM_Channel == (u16)TIM_Channel_2))
\ 0000000E 4C88 LDRH R4,[R1, #+2]
\ 00000010 002C CMP R4,#+0
\ 00000012 02D0 BEQ.N ??TIM_OCInit_0
\ 00000014 4C88 LDRH R4,[R1, #+2]
\ 00000016 012C CMP R4,#+1
\ 00000018 32D1 BNE.N ??TIM_OCInit_1
196 {
197 tmpccmrx = TIMx->CCMR1;
\ ??TIM_OCInit_0:
\ 0000001A 048B LDRH R4,[R0, #+24]
\ 0000001C 2200 MOVS R2,R4
198
199 /* Reset the Output Compare Bits */
200 tmpccmrx &= Tab_OCModeMask[TIM_OCInitStruct->TIM_Channel];
\ 0000001E 1500 MOVS R5,R2
\ 00000020 4A88 LDRH R2,[R1, #+2]
\ 00000022 0224 MOVS R4,#+2
\ 00000024 6243 MULS R2,R4,R2
\ 00000026 354C LDR.N R4,??TIM_OCInit_2 ;; Tab_OCModeMask
\ 00000028 A25A LDRH R2,[R4, R2]
\ 0000002A 2A40 ANDS R2,R2,R5
201
202 /* Set the Output Polarity level */
203 tmpccer &= Tab_PolarityMask[TIM_OCInitStruct->TIM_Channel];
\ 0000002C 1D00 MOVS R5,R3
\ 0000002E 4B88 LDRH R3,[R1, #+2]
\ 00000030 0224 MOVS R4,#+2
\ 00000032 6343 MULS R3,R4,R3
\ 00000034 324C LDR.N R4,??TIM_OCInit_2+0x4 ;; Tab_PolarityMask
\ 00000036 E35A LDRH R3,[R4, R3]
\ 00000038 2B40 ANDS R3,R3,R5
204
205 if (TIM_OCInitStruct->TIM_Channel == TIM_Channel_1)
\ 0000003A 4C88 LDRH R4,[R1, #+2]
\ 0000003C 002C CMP R4,#+0
\ 0000003E 0ED1 BNE.N ??TIM_OCInit_3
206 {
207 /* Disable the Channel 1: Reset the CCE Bit */
208 TIMx->CCER &= CCER_CC1E_Reset;
\ 00000040 048C LDRH R4,[R0, #+32]
\ 00000042 .... LDR.N R5,??DataTable0 ;; 0x3332
\ 00000044 2540 ANDS R5,R5,R4
\ 00000046 0584 STRH R5,[R0, #+32]
209
210 /* Select the Output Compare Mode */
211 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
\ 00000048 1400 MOVS R4,R2
\ 0000004A 0A88 LDRH R2,[R1, #+0]
\ 0000004C 2243 ORRS R2,R2,R4
212
213 /* Set the Capture Compare Register value */
214 TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
\ 0000004E 8C88 LDRH R4,[R1, #+4]
\ 00000050 8486 STRH R4,[R0, #+52]
215
216 /* Set the Capture Compare Enable Bit */
217 tmpccer |= CCER_CC1E_Set;
\ 00000052 53F00103 ORRS R3,R3,#0x1
218
219 /* Set the Capture Compare Polarity */
220 tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
\ 00000056 1C00 MOVS R4,R3
\ 00000058 CB88 LDRH R3,[R1, #+6]
\ 0000005A 2343 ORRS R3,R3,R4
\ 0000005C 0DE0 B.N ??TIM_OCInit_4
221 }
222 else /* TIM_Channel_2 */
223 {
224 /* Disable the Channel 2: Reset the CCE Bit */
225 TIMx->CCER &= CCER_CC2E_Reset;
\ ??TIM_OCInit_3:
\ 0000005E 048C LDRH R4,[R0, #+32]
\ 00000060 .... LDR.N R5,??DataTable1 ;; 0x3323
\ 00000062 2540 ANDS R5,R5,R4
\ 00000064 0584 STRH R5,[R0, #+32]
226
227 /* Select the Output Compare Mode */
228 tmpccmrx |= (u32)TIM_OCInitStruct->TIM_OCMode << 8;
\ 00000066 0C88 LDRH R4,[R1, #+0]
\ 00000068 52EA0422 ORRS R2,R2,R4, LSL #+8
229
230 /* Set the Capture Compare Register value */
231 TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
\ 0000006C 8C88 LDRH R4,[R1, #+4]
\ 0000006E 0487 STRH R4,[R0, #+56]
232
233 /* Set the Capture Compare Enable Bit */
234 tmpccer |= CCER_CC2E_Set;
\ 00000070 53F01003 ORRS R3,R3,#0x10
235
236 /* Set the Capture Compare Polarity */
237 tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 4;
\ 00000074 CC88 LDRH R4,[R1, #+6]
\ 00000076 53EA0413 ORRS R3,R3,R4, LSL #+4
238 }
239
240 TIMx->CCMR1 = (u16)tmpccmrx;
\ ??TIM_OCInit_4:
\ 0000007A 1400 MOVS R4,R2
\ 0000007C 0483 STRH R4,[R0, #+24]
\ 0000007E 38E0 B.N ??TIM_OCInit_5
241 }
242 else
243 {
244 if ((TIM_OCInitStruct->TIM_Channel == TIM_Channel_3) ||
245 (TIM_OCInitStruct->TIM_Channel == TIM_Channel_4))
\ ??TIM_OCInit_1:
\ 00000080 4C88 LDRH R4,[R1, #+2]
\ 00000082 022C CMP R4,#+2
\ 00000084 02D0 BEQ.N ??TIM_OCInit_6
\ 00000086 4C88 LDRH R4,[R1, #+2]
\ 00000088 032C CMP R4,#+3
\ 0000008A 32D1 BNE.N ??TIM_OCInit_5
246 {
247 tmpccmrx = TIMx->CCMR2;
\ ??TIM_OCInit_6:
\ 0000008C 848B LDRH R4,[R0, #+28]
\ 0000008E 2200 MOVS R2,R4
248
249 /* Reset the Output Compare Bits */
250 tmpccmrx &= Tab_OCModeMask[TIM_OCInitStruct->TIM_Channel];
\ 00000090 1500 MOVS R5,R2
\ 00000092 4A88 LDRH R2,[R1, #+2]
\ 00000094 0224 MOVS R4,#+2
\ 00000096 6243 MULS R2,R4,R2
\ 00000098 184C LDR.N R4,??TIM_OCInit_2 ;; Tab_OCModeMask
\ 0000009A A25A LDRH R2,[R4, R2]
\ 0000009C 2A40 ANDS R2,R2,R5
251
252 /* Set the Output Polarity level */
253 tmpccer &= Tab_PolarityMask[TIM_OCInitStruct->TIM_Channel];
\ 0000009E 1D00 MOVS R5,R3
\ 000000A0 4B88 LDRH R3,[R1, #+2]
\ 000000A2 0224 MOVS R4,#+2
\ 000000A4 6343 MULS R3,R4,R3
\ 000000A6 164C LDR.N R4,??TIM_OCInit_2+0x4 ;; Tab_PolarityMask
\ 000000A8 E35A LDRH R3,[R4, R3]
\ 000000AA 2B40 ANDS R3,R3,R5
254
255 if (TIM_OCInitStruct->TIM_Channel == TIM_Channel_3)
\ 000000AC 4C88 LDRH R4,[R1, #+2]
\ 000000AE 022C CMP R4,#+2
\ 000000B0 0ED1 BNE.N ??TIM_OCInit_7
256 {
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