📄 stm32f10x_can.lst
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###############################################################################
# #
# 10/Jun/2008 15:11:05 #
# IAR ARM ANSI C/C++ Compiler V5.11.0.20622/W32 EVALUATION #
# Copyright 1999-2007 IAR Systems. All rights reserved. #
# #
# Cpu mode = thumb #
# Endian = little #
# Source file = E:\library\src\stm32f10x_can.c #
# Command line = E:\library\src\stm32f10x_can.c -lcN #
# E:\ELE\yten\pro\Debug\List\ -o #
# E:\ELE\yten\pro\Debug\Obj\ --debug --endian little #
# --cpu Cortex-M3 -e --fpu None --dlib_config #
# D:\IARARM\ARM\INC\DLib_Config_Normal.h -I #
# E:\ELE\yten\pro\ -I E:\ELE\yten\pro\..\LIBRARY\INC\ -I #
# D:\IARARM\ARM\INC\ -Oh #
# List file = E:\ELE\yten\pro\Debug\List\stm32f10x_can.lst #
# Object file = E:\ELE\yten\pro\Debug\Obj\stm32f10x_can.o #
# #
# #
###############################################################################
E:\library\src\stm32f10x_can.c
1 /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
2 * File Name : stm32f10x_can.c
3 * Author : MCD Application Team
4 * Version : V1.0
5 * Date : 10/08/2007
6 * Description : This file provides all the CAN firmware functions.
7 ********************************************************************************
8 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
9 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
10 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
11 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
12 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
13 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
14 *******************************************************************************/
15
16 /* Includes ------------------------------------------------------------------*/
17 #include "stm32f10x_can.h"
18 #include "stm32f10x_rcc.h"
19
20 /* Private typedef -----------------------------------------------------------*/
21
22 /* Private define ------------------------------------------------------------*/
23 /* CAN Master Control Register bits */
24 #define CAN_MCR_INRQ ((u32)0x00000001) /* Initialization request */
25 #define CAN_MCR_SLEEP ((u32)0x00000002) /* Sleep mode request */
26 #define CAN_MCR_TXFP ((u32)0x00000004) /* Transmit FIFO priority */
27 #define CAN_MCR_RFLM ((u32)0x00000008) /* Receive FIFO locked mode */
28 #define CAN_MCR_NART ((u32)0x00000010) /* No automatic retransmission */
29 #define CAN_MCR_AWUM ((u32)0x00000020) /* Automatic wake up mode */
30 #define CAN_MCR_ABOM ((u32)0x00000040) /* Automatic bus-off management */
31 #define CAN_MCR_TTCM ((u32)0x00000080) /* time triggered communication */
32
33 /* CAN Master Status Register bits */
34 #define CAN_MSR_INAK ((u32)0x00000001) /* Initialization acknowledge */
35 #define CAN_MSR_WKUI ((u32)0x00000008) /* Wake-up interrupt */
36 #define CAN_MSR_SLAKI ((u32)0x00000010) /* Sleep acknowledge interrupt */
37
38 /* CAN Transmit Status Register bits */
39 #define CAN_TSR_RQCP0 ((u32)0x00000001) /* Request completed mailbox0 */
40 #define CAN_TSR_TXOK0 ((u32)0x00000002) /* Transmission OK of mailbox0 */
41 #define CAN_TSR_ABRQ0 ((u32)0x00000080) /* Abort request for mailbox0 */
42 #define CAN_TSR_RQCP1 ((u32)0x00000100) /* Request completed mailbox1 */
43 #define CAN_TSR_TXOK1 ((u32)0x00000200) /* Transmission OK of mailbox1 */
44 #define CAN_TSR_ABRQ1 ((u32)0x00008000) /* Abort request for mailbox1 */
45 #define CAN_TSR_RQCP2 ((u32)0x00010000) /* Request completed mailbox2 */
46 #define CAN_TSR_TXOK2 ((u32)0x00020000) /* Transmission OK of mailbox2 */
47 #define CAN_TSR_ABRQ2 ((u32)0x00800000) /* Abort request for mailbox2 */
48 #define CAN_TSR_TME0 ((u32)0x04000000) /* Transmit mailbox 0 empty */
49 #define CAN_TSR_TME1 ((u32)0x08000000) /* Transmit mailbox 1 empty */
50 #define CAN_TSR_TME2 ((u32)0x10000000) /* Transmit mailbox 2 empty */
51
52 /* CAN Receive FIFO 0 Register bits */
53 #define CAN_RF0R_FULL0 ((u32)0x00000008) /* FIFO 0 full */
54 #define CAN_RF0R_FOVR0 ((u32)0x00000010) /* FIFO 0 overrun */
55 #define CAN_RF0R_RFOM0 ((u32)0x00000020) /* Release FIFO 0 output mailbox */
56
57 /* CAN Receive FIFO 1 Register bits */
58 #define CAN_RF1R_FULL1 ((u32)0x00000008) /* FIFO 1 full */
59 #define CAN_RF1R_FOVR1 ((u32)0x00000010) /* FIFO 1 overrun */
60 #define CAN_RF1R_RFOM1 ((u32)0x00000020) /* Release FIFO 1 output mailbox */
61
62 /* CAN Error Status Register bits */
63 #define CAN_ESR_EWGF ((u32)0x00000001) /* Error warning flag */
64 #define CAN_ESR_EPVF ((u32)0x00000002) /* Error passive flag */
65 #define CAN_ESR_BOFF ((u32)0x00000004) /* Bus-off flag */
66
67 /* CAN Mailbox Transmit Request */
68 #define CAN_TMIDxR_TXRQ ((u32)0x00000001) /* Transmit mailbox request */
69
70 /* CAN Filter Master Register bits */
71 #define CAN_FMR_FINIT ((u32)0x00000001) /* Filter init mode */
72
73
74 /* Private macro -------------------------------------------------------------*/
75 /* Private variables ---------------------------------------------------------*/
76 /* Private function prototypes -----------------------------------------------*/
77 static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit);
78
79 /* Private functions ---------------------------------------------------------*/
80 /*******************************************************************************
81 * Function Name : CAN_DeInit
82 * Description : Deinitializes the CAN peripheral registers to their default
83 * reset values.
84 * Input : None.
85 * Output : None.
86 * Return : None.
87 *******************************************************************************/
88 void CAN_DeInit(void)
89 {
90 /* Enable CAN reset state */
91 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, ENABLE);
92 /* Release CAN from reset state */
93 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, DISABLE);
94 }
95
96 /*******************************************************************************
97 * Function Name : CAN_Init
98 * Description : Initializes the CAN peripheral according to the specified
99 * parameters in the CAN_InitStruct.
100 * Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
101 contains the configuration information for the CAN peripheral.
102 * Output : None.
103 * Return : Constant indicates initialization succeed which will be
104 * CANINITFAILED or CANINITOK.
105 *******************************************************************************/
106 u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct)
107 {
108 u8 InitStatus = 0;
109
110 /* Check the parameters */
111 assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
112 assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
113 assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
114 assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
115 assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
116 assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
117 assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
118 assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
119 assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
120 assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
121 assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
122
123 /* Request initialisation */
124 CAN->MCR = CAN_MCR_INRQ;
125
126 /* ...and check acknowledged */
127 if ((CAN->MSR & CAN_MSR_INAK) == 0)
128 {
129 InitStatus = CANINITFAILED;
130 }
131 else
132 {
133 /* Set the time triggered communication mode */
134 if (CAN_InitStruct->CAN_TTCM == ENABLE)
135 {
136 CAN->MCR |= CAN_MCR_TTCM;
137 }
138 else
139 {
140 CAN->MCR &= ~CAN_MCR_TTCM;
141 }
142
143 /* Set the automatic bus-off management */
144 if (CAN_InitStruct->CAN_ABOM == ENABLE)
145 {
146 CAN->MCR |= CAN_MCR_ABOM;
147 }
148 else
149 {
150 CAN->MCR &= ~CAN_MCR_ABOM;
151 }
152
153 /* Set the automatic wake-up mode */
154 if (CAN_InitStruct->CAN_AWUM == ENABLE)
155 {
156 CAN->MCR |= CAN_MCR_AWUM;
157 }
158 else
159 {
160 CAN->MCR &= ~CAN_MCR_AWUM;
161 }
162
163 /* Set the no automatic retransmission */
164 if (CAN_InitStruct->CAN_NART == ENABLE)
165 {
166 CAN->MCR |= CAN_MCR_NART;
167 }
168 else
169 {
170 CAN->MCR &= ~CAN_MCR_NART;
171 }
172
173 /* Set the receive FIFO locked mode */
174 if (CAN_InitStruct->CAN_RFLM == ENABLE)
175 {
176 CAN->MCR |= CAN_MCR_RFLM;
177 }
178 else
179 {
180 CAN->MCR &= ~CAN_MCR_RFLM;
181 }
182
183 /* Set the transmit FIFO priority */
184 if (CAN_InitStruct->CAN_TXFP == ENABLE)
185 {
186 CAN->MCR |= CAN_MCR_TXFP;
187 }
188 else
189 {
190 CAN->MCR &= ~CAN_MCR_TXFP;
191 }
192
193 /* Set the bit timing register */
194 CAN->BTR = (u32)((u32)CAN_InitStruct->CAN_Mode << 30) | ((u32)CAN_InitStruct->CAN_SJW << 24) |
195 ((u32)CAN_InitStruct->CAN_BS1 << 16) | ((u32)CAN_InitStruct->CAN_BS2 << 20) |
196 ((u32)CAN_InitStruct->CAN_Prescaler - 1);
197
198 InitStatus = CANINITOK;
199
200 /* Request leave initialisation */
201 CAN->MCR &= ~CAN_MCR_INRQ;
202
203 /* ...and check acknowledged */
204 if ((CAN->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
205 {
206 InitStatus = CANINITFAILED;
207 }
208 }
209
210 /* At this step, return the status of initialization */
211 return InitStatus;
212 }
213
214 /*******************************************************************************
215 * Function Name : CAN_FilterInit
216 * Description : Initializes the CAN peripheral according to the specified
217 * parameters in the CAN_FilterInitStruct.
218 * Input : CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef
219 * structure that contains the configuration information.
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