📄 stm32f10x_usart.lst
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# #
# 30/Jul/2008 11:02:25 #
# IAR ARM ANSI C/C++ Compiler V5.11.0.20622/W32 EVALUATION #
# Copyright 1999-2007 IAR Systems. All rights reserved. #
# #
# Cpu mode = thumb #
# Endian = little #
# Source file = E:\library\src\stm32f10x_usart.c #
# Command line = E:\library\src\stm32f10x_usart.c -D EMB_FLASH -lcN #
# E:\ELE\yten\pro\Release\List\ -o #
# E:\ELE\yten\pro\Release\Obj\ --no_cse --no_unroll #
# --no_inline --no_code_motion --no_tbaa --no_clustering #
# --no_scheduling --debug --endian little --cpu Cortex-M3 #
# -e --fpu None --dlib_config "C:\Program Files\IAR #
# Systems\Embedded Workbench 5.0 #
# Evaluation\ARM\INC\DLib_Config_Normal.h" -I #
# E:\ELE\yten\pro\ -I E:\ELE\yten\pro\..\LIBRARY\INC\ -I #
# "C:\Program Files\IAR Systems\Embedded Workbench 5.0 #
# Evaluation\ARM\INC\" -On #
# List file = E:\ELE\yten\pro\Release\List\stm32f10x_usart.lst #
# Object file = E:\ELE\yten\pro\Release\Obj\stm32f10x_usart.o #
# #
# #
###############################################################################
E:\library\src\stm32f10x_usart.c
1 /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
2 * File Name : stm32f10x_usart.c
3 * Author : MCD Application Team
4 * Version : V1.0
5 * Date : 10/08/2007
6 * Description : This file provides all the USART firmware functions.
7 ********************************************************************************
8 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
9 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
10 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
11 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
12 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
13 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
14 *******************************************************************************/
15
16 /* Includes ------------------------------------------------------------------*/
17 #include "stm32f10x_usart.h"
18 #include "stm32f10x_rcc.h"
19
20 /* Private typedef -----------------------------------------------------------*/
21 /* Private define ------------------------------------------------------------*/
22 /* USART RUN Mask */
23 #define CR1_RUN_Set ((u16)0x2000) /* USART Enable Mask */
24 #define CR1_RUN_Reset ((u16)0xDFFF) /* USART Disable Mask */
25
26 #define CR2_Address_Mask ((u16)0xFFF0) /* USART address Mask */
27
28 /* USART RWU Mask */
29 #define CR1_RWU_Set ((u16)0x0002) /* USART mute mode Enable Mask */
30 #define CR1_RWU_Reset ((u16)0xFFFD) /* USART mute mode Enable Mask */
31
32 #define USART_IT_Mask ((u16)0x001F) /* USART Interrupt Mask */
33
34 /* USART LIN Mask */
35 #define CR2_LINE_Set ((u16)0x4000) /* USART LIN Enable Mask */
36 #define CR2_LINE_Reset ((u16)0xBFFF) /* USART LIN Disable Mask */
37
38 #define CR1_SBK_Set ((u16)0x0001) /* USART Break Character send Mask */
39
40 /* USART SC Mask */
41 #define CR3_SCEN_Set ((u16)0x0020) /* USART SC Enable Mask */
42 #define CR3_SCEN_Reset ((u16)0xFFDF) /* USART SC Disable Mask */
43
44 /* USART SC NACK Mask */
45 #define CR3_NACK_Set ((u16)0x0010) /* USART SC NACK Enable Mask */
46 #define CR3_NACK_Reset ((u16)0xFFEF) /* USART SC NACK Disable Mask */
47
48 /* USART Half-Duplex Mask */
49 #define CR3_HDSEL_Set ((u16)0x0008) /* USART Half-Duplex Enable Mask */
50 #define CR3_HDSEL_Reset ((u16)0xFFF7) /* USART Half-Duplex Disable Mask */
51
52 /* USART IrDA Mask */
53 #define CR3_IRLP_Mask ((u16)0xFFFB) /* USART IrDA LowPower mode Mask */
54
55 /* USART LIN Break detection */
56 #define CR3_LBDL_Mask ((u16)0xFFDF) /* USART LIN Break detection Mask */
57
58 /* USART WakeUp Method */
59 #define CR3_WAKE_Mask ((u16)0xF7FF) /* USART WakeUp Method Mask */
60
61 /* USART IrDA Mask */
62 #define CR3_IREN_Set ((u16)0x0002) /* USART IrDA Enable Mask */
63 #define CR3_IREN_Reset ((u16)0xFFFD) /* USART IrDA Disable Mask */
64
65 #define GTPR_LSB_Mask ((u16)0x00FF) /* Guard Time Register LSB Mask */
66 #define GTPR_MSB_Mask ((u16)0xFF00) /* Guard Time Register MSB Mask */
67
68 #define CR1_CLEAR_Mask ((u16)0xE9F3) /* USART CR1 Mask */
69 #define CR2_CLEAR_Mask ((u16)0xC0FF) /* USART CR2 Mask */
70 #define CR3_CLEAR_Mask ((u16)0xFCFF) /* USART CR3 Mask */
71
72
73 /* Private macro -------------------------------------------------------------*/
74 /* Private variables ---------------------------------------------------------*/
75 /* Private function prototypes -----------------------------------------------*/
76 /* Private functions ---------------------------------------------------------*/
77
78 /*******************************************************************************
79 * Function Name : USART_DeInit
80 * Description : Deinitializes the USARTx peripheral registers to their
81 * default reset values.
82 * Input : - USARTx: where x can be 1, 2 or 3 to select the USART
83 * peripheral.
84 * Output : None
85 * Return : None
86 *******************************************************************************/
87 void USART_DeInit(USART_TypeDef* USARTx)
88 {
89 switch (*(u32*)&USARTx)
90 {
91 case USART1_BASE:
92 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
93 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
94 break;
95
96 case USART2_BASE:
97 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
98 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
99 break;
100
101 case USART3_BASE:
102 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
103 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
104 break;
105
106 default:
107 break;
108 }
109 }
110
111 /*******************************************************************************
112 * Function Name : USART_Init
113 * Description : Initializes the USARTx peripheral according to the specified
114 * parameters in the USART_InitStruct .
115 * Input : - USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
116 * - USART_InitStruct: pointer to a USART_InitTypeDef structure
117 * that contains the configuration information for the
118 * specified USART peripheral.
119 * Output : None
120 * Return : None
121 *******************************************************************************/
122 void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
123 {
124 u32 tmpreg = 0x00, apbclock = 0x00;
125 u32 integerdivider = 0x00;
126 u32 fractionaldivider = 0x00;
127 RCC_ClocksTypeDef RCC_ClocksStatus;
128
129 /* Check the parameters */
130 assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
131 assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
132 assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
133 assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
134 assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
135 assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
136 assert_param(IS_USART_CLOCK(USART_InitStruct->USART_Clock));
137 assert_param(IS_USART_CPOL(USART_InitStruct->USART_CPOL));
138 assert_param(IS_USART_CPHA(USART_InitStruct->USART_CPHA));
139 assert_param(IS_USART_LASTBIT(USART_InitStruct->USART_LastBit));
140
141 /*---------------------------- USART CR2 Configuration -----------------------*/
142 tmpreg = USARTx->CR2;
143 /* Clear STOP[13:12], CLKEN, CPOL, CPHA and LBCL bits */
144 tmpreg &= CR2_CLEAR_Mask;
145
146 /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
147 /* Set STOP[13:12] bits according to USART_Mode value */
148 /* Set CPOL bit according to USART_CPOL value */
149 /* Set CPHA bit according to USART_CPHA value */
150 /* Set LBCL bit according to USART_LastBit value */
151 tmpreg |= (u32)USART_InitStruct->USART_StopBits | USART_InitStruct->USART_Clock |
152 USART_InitStruct->USART_CPOL | USART_InitStruct->USART_CPHA |
153 USART_InitStruct->USART_LastBit;
154
155 /* Write to USART CR2 */
156 USARTx->CR2 = (u16)tmpreg;
157
158 /*---------------------------- USART CR1 Configuration -----------------------*/
159 tmpreg = 0x00;
160 tmpreg = USARTx->CR1;
161 /* Clear M, PCE, PS, TE and RE bits */
162 tmpreg &= CR1_CLEAR_Mask;
163
164 /* Configure the USART Word Length, Parity and mode ----------------------- */
165 /* Set the M bits according to USART_WordLength value */
166 /* Set PCE and PS bits according to USART_Parity value */
167 /* Set TE and RE bits according to USART_Mode value */
168 tmpreg |= (u32)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
169 USART_InitStruct->USART_Mode;
170
171 /* Write to USART CR1 */
172 USARTx->CR1 = (u16)tmpreg;
173
174 /*---------------------------- USART CR3 Configuration -----------------------*/
175 tmpreg = 0x00;
176 tmpreg = USARTx->CR3;
177 /* Clear CTSE and RTSE bits */
178 tmpreg &= CR3_CLEAR_Mask;
179
180 /* Configure the USART HFC -------------------------------------------------*/
181 /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
182 tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
183
184 /* Write to USART CR3 */
185 USARTx->CR3 = (u16)tmpreg;
186
187 /*---------------------------- USART BRR Configuration -----------------------*/
188 tmpreg = 0x00;
189
190 /* Configure the USART Baud Rate -------------------------------------------*/
191 RCC_GetClocksFreq(&RCC_ClocksStatus);
192 if ((*(u32*)&USARTx) == USART1_BASE)
193 {
194 apbclock = RCC_ClocksStatus.PCLK2_Frequency;
195 }
196 else
197 {
198 apbclock = RCC_ClocksStatus.PCLK1_Frequency;
199 }
200
201 /* Determine the integer part */
202 integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate)));
203 tmpreg = (integerdivider / 0x64) << 0x04;
204
205 /* Determine the fractional part */
206 fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04));
207 tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((u8)0x0F);
208
209 /* Write to USART BRR */
210 USARTx->BRR = (u16)tmpreg;
211 }
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