📄 stm32f10x_adc.lst
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418 assert_param(IS_FUNCTIONAL_STATE(NewState));
419
420 if (NewState != DISABLE)
421 {
422 /* Enable the selected ADC conversion on external event */
423 /* Starts the selected ADC conversion */
424 ADCx->CR2 |= CR2_EXTTRIG_SWSTRT_Set;
425 }
426 else
427 {
428 /* Stops the selected ADC conversion */
429 /* Disable the selected ADC conversion on external event */
430 ADCx->CR2 &= CR2_EXTTRIG_SWSTRT_Reset;
431 }
432 }
433
434 /*******************************************************************************
435 * Function Name : ADC_GetSoftwareStartConvStatus
436 * Description : Gets the selected ADC Software start conversion Status.
437 * Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
438 * Output : None
439 * Return : The new state of ADC software start conversion (SET or RESET).
440 *******************************************************************************/
441 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
442 {
443 FlagStatus bitstatus = RESET;
444
445 /* Check the status of SWSTRT bit */
446 if ((ADCx->CR2 & CR2_SWSTRT_Set) != (u32)RESET)
447 {
448 /* SWSTRT bit is set */
449 bitstatus = SET;
450 }
451 else
452 {
453 /* SWSTRT bit is reset */
454 bitstatus = RESET;
455 }
456 /* Return the SWSTRT bit status */
457 return bitstatus;
458 }
459
460 /*******************************************************************************
461 * Function Name : ADC_DiscModeChannelCountConfig
462 * Description : Configures the discontinuous mode for the selected ADC regular
463 * group channel.
464 * Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
465 * - Number: specifies the discontinuous mode regular channel
466 * count value. This number must be between 1 and 8.
467 * Output : None
468 * Return : None
469 *******************************************************************************/
470 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number)
471 {
472 u32 tmpreg1 = 0;
473 u8 tmpreg2 = 0;
474
475 /* Check the parameters */
476 assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
477
478 /* Get the old register value */
479 tmpreg1 = ADCx->CR1;
480 /* Clear the old discontinuous mode channel count */
481 tmpreg1 &= CR1_DISCNUM_Reset;
482 /* Set the discontinuous mode channel count */
483 tmpreg2 = Number - 1;
484 tmpreg1 |= ((u32)tmpreg2 << 13);
485 /* Store the new register value */
486 ADCx->CR1 = tmpreg1;
487 }
488
489 /*******************************************************************************
490 * Function Name : ADC_DiscModeCmd
491 * Description : Enables or disables the discontinuous mode on regular group
492 * channel for the specified ADC
493 * Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
494 * - NewState: new state of the selected ADC discontinuous mode
495 * on regular group channel.
496 * This parameter can be: ENABLE or DISABLE.
497 * Output : None
498 * Return : None
499 *******************************************************************************/
500 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
501 {
502 /* Check the parameters */
503 assert_param(IS_FUNCTIONAL_STATE(NewState));
504
505 if (NewState != DISABLE)
506 {
507 /* Enable the selected ADC regular discontinuous mode */
508 ADCx->CR1 |= CR1_DISCEN_Set;
509 }
510 else
511 {
512 /* Disable the selected ADC regular discontinuous mode */
513 ADCx->CR1 &= CR1_DISCEN_Reset;
514 }
515 }
516
517 /*******************************************************************************
518 * Function Name : ADC_RegularChannelConfig
519 * Description : Configures for the selected ADC regular channel its corresponding
520 * rank in the sequencer and its sample time.
521 * Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
522 * - ADC_Channel: the ADC channel to configure.
523 * This parameter can be one of the following values:
524 * - ADC_Channel_0: ADC Channel0 selected
525 * - ADC_Channel_1: ADC Channel1 selected
526 * - ADC_Channel_2: ADC Channel2 selected
527 * - ADC_Channel_3: ADC Channel3 selected
528 * - ADC_Channel_4: ADC Channel4 selected
529 * - ADC_Channel_5: ADC Channel5 selected
530 * - ADC_Channel_6: ADC Channel6 selected
531 * - ADC_Channel_7: ADC Channel7 selected
532 * - ADC_Channel_8: ADC Channel8 selected
533 * - ADC_Channel_9: ADC Channel9 selected
534 * - ADC_Channel_10: ADC Channel10 selected
535 * - ADC_Channel_11: ADC Channel11 selected
536 * - ADC_Channel_12: ADC Channel12 selected
537 * - ADC_Channel_13: ADC Channel13 selected
538 * - ADC_Channel_14: ADC Channel14 selected
539 * - ADC_Channel_15: ADC Channel15 selected
540 * - ADC_Channel_16: ADC Channel16 selected
541 * - ADC_Channel_17: ADC Channel17 selected
542 * - Rank: The rank in the regular group sequencer. This parameter
543 * must be between 1 to 16.
544 * - ADC_SampleTime: The sample time value to be set for the
545 * selected channel.
546 * This parameter can be one of the following values:
547 * - ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
548 * - ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
549 * - ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
550 * - ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
551 * - ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
552 * - ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
553 * - ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
554 * - ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
555 * Output : None
556 * Return : None
557 *******************************************************************************/
558 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime)
559 {
560 u32 tmpreg1 = 0, tmpreg2 = 0;
561
562 /* Check the parameters */
563 assert_param(IS_ADC_CHANNEL(ADC_Channel));
564 assert_param(IS_ADC_REGULAR_RANK(Rank));
565 assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
566
567 /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
568 if (ADC_Channel > ADC_Channel_9)
569 {
570 /* Get the old register value */
571 tmpreg1 = ADCx->SMPR1;
572 /* Calculate the mask to clear */
573 tmpreg2 = (u32)SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
574 /* Clear the old discontinuous mode channel count */
575 tmpreg1 &= ~tmpreg2;
576 /* Calculate the mask to set */
577 tmpreg2 = (u32)ADC_SampleTime << (3 * (ADC_Channel - 10));
578 /* Set the discontinuous mode channel count */
579 tmpreg1 |= tmpreg2;
580 /* Store the new register value */
581 ADCx->SMPR1 = tmpreg1;
582 }
583 else /* ADC_Channel include in ADC_Channel_[0..9] */
584 {
585 /* Get the old register value */
586 tmpreg1 = ADCx->SMPR2;
587 /* Calculate the mask to clear */
588 tmpreg2 = (u32)SMPR2_SMP_Set << (3 * ADC_Channel);
589 /* Clear the old discontinuous mode channel count */
590 tmpreg1 &= ~tmpreg2;
591 /* Calculate the mask to set */
592 tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel);
593 /* Set the discontinuous mode channel count */
594 tmpreg1 |= tmpreg2;
595 /* Store the new register value */
596 ADCx->SMPR2 = tmpreg1;
597 }
598 /* For Rank 1 to 6 */
599 if (Rank < 7)
600 {
601 /* Get the old register value */
602 tmpreg1 = ADCx->SQR3;
603 /* Calculate the mask to clear */
604 tmpreg2 = (u32)SQR3_SQ_Set << (5 * (Rank - 1));
605 /* Clear the old SQx bits for the selected rank */
606 tmpreg1 &= ~tmpreg2;
607 /* Calculate the mask to set */
608 tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 1));
609 /* Set the SQx bits for the selected rank */
610 tmpreg1 |= tmpreg2;
611 /* Store the new register value */
612 ADCx->SQR3 = tmpreg1;
613 }
614 /* For Rank 7 to 12 */
615 else if (Rank < 13)
616 {
617 /* Get the old register value */
618 tmpreg1 = ADCx->SQR2;
619 /* Calculate the mask to clear */
620 tmpreg2 = (u32)SQR2_SQ_Set << (5 * (Rank - 7));
621 /* Clear the old SQx bits for the selected rank */
622 tmpreg1 &= ~tmpreg2;
623 /* Calculate the mask to set */
624 tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 7));
625 /* Set the SQx bits for the selected rank */
626 tmpreg1 |= tmpreg2;
627 /* Store the new register value */
628 ADCx->SQR2 = tmpreg1;
629 }
630 /* For Rank 13 to 16 */
631 else
632 {
633 /* Get the old register value */
634 tmpreg1 = ADCx->SQR1;
635 /* Calculate the mask to clear */
636 tmpreg2 = (u32)SQR1_SQ_Set << (5 * (Rank - 13));
637 /* Clear the old SQx bits for the selected rank */
638 tmpreg1 &= ~tmpreg2;
639 /* Calculate the mask to set */
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