📄 stm32f10x_adc.lst
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# #
# 30/Jul/2008 11:02:23 #
# IAR ARM ANSI C/C++ Compiler V5.11.0.20622/W32 EVALUATION #
# Copyright 1999-2007 IAR Systems. All rights reserved. #
# #
# Cpu mode = thumb #
# Endian = little #
# Source file = E:\library\src\stm32f10x_adc.c #
# Command line = E:\library\src\stm32f10x_adc.c -D EMB_FLASH -lcN #
# E:\ELE\yten\pro\Release\List\ -o #
# E:\ELE\yten\pro\Release\Obj\ --no_cse --no_unroll #
# --no_inline --no_code_motion --no_tbaa --no_clustering #
# --no_scheduling --debug --endian little --cpu Cortex-M3 #
# -e --fpu None --dlib_config "C:\Program Files\IAR #
# Systems\Embedded Workbench 5.0 #
# Evaluation\ARM\INC\DLib_Config_Normal.h" -I #
# E:\ELE\yten\pro\ -I E:\ELE\yten\pro\..\LIBRARY\INC\ -I #
# "C:\Program Files\IAR Systems\Embedded Workbench 5.0 #
# Evaluation\ARM\INC\" -On #
# List file = E:\ELE\yten\pro\Release\List\stm32f10x_adc.lst #
# Object file = E:\ELE\yten\pro\Release\Obj\stm32f10x_adc.o #
# #
# #
###############################################################################
E:\library\src\stm32f10x_adc.c
1 /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
2 * File Name : stm32f10x_adc.c
3 * Author : MCD Application Team
4 * Version : V1.0
5 * Date : 10/08/2007
6 * Description : This file provides all the ADC firmware functions.
7 ********************************************************************************
8 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
9 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
10 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
11 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
12 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
13 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
14 *******************************************************************************/
15
16 /* Includes ------------------------------------------------------------------*/
17 #include "stm32f10x_adc.h"
18 #include "stm32f10x_rcc.h"
19
20 /* Private typedef -----------------------------------------------------------*/
21 /* Private define ------------------------------------------------------------*/
22 /* ADC ADON mask */
23 #define CR2_ADON_Set ((u32)0x00000001)
24 #define CR2_ADON_Reset ((u32)0xFFFFFFFE)
25
26 /* ADC DMA mask */
27 #define CR2_DMA_Set ((u16)0x0100)
28 #define CR2_DMA_Reset ((u16)0xFEFF)
29
30 /* ADC RSTCAL mask */
31 #define CR2_RSTCAL_Set ((u16)0x0008)
32
33 /* ADC CAL mask */
34 #define CR2_CAL_Set ((u16)0x0004)
35
36 /* ADC SWSTRT mask */
37 #define CR2_SWSTRT_Set ((u32)0x00400000)
38
39 /* ADC DISCNUM mask */
40 #define CR1_DISCNUM_Reset ((u32)0xFFFF1FFF)
41
42 /* ADC DISCEN mask */
43 #define CR1_DISCEN_Set ((u32)0x00000800)
44 #define CR1_DISCEN_Reset ((u32)0xFFFFF7FF)
45
46 /* ADC EXTTRIG mask */
47 #define CR2_EXTTRIG_Set ((u32)0x00100000)
48 #define CR2_EXTTRIG_Reset ((u32)0xFFEFFFFF)
49
50 /* ADC Software start mask */
51 #define CR2_EXTTRIG_SWSTRT_Set ((u32)0x00500000)
52 #define CR2_EXTTRIG_SWSTRT_Reset ((u32)0xFFAFFFFF)
53
54 /* ADC JAUTO mask */
55 #define CR1_JAUTO_Set ((u32)0x00000400)
56 #define CR1_JAUTO_Reset ((u32)0xFFFFFBFF)
57
58 /* ADC JDISCEN mask */
59 #define CR1_JDISCEN_Set ((u32)0x00001000)
60 #define CR1_JDISCEN_Reset ((u32)0xFFFFEFFF)
61
62 /* ADC JEXTSEL mask */
63 #define CR2_JEXTSEL_Reset ((u32)0xFFFF8FFF)
64
65 /* ADC JEXTTRIG mask */
66 #define CR2_JEXTTRIG_Set ((u32)0x00008000)
67 #define CR2_JEXTTRIG_Reset ((u32)0xFFFF7FFF)
68
69 /* ADC JSWSTRT mask */
70 #define CR2_JSWSTRT_Set ((u32)0x00200000)
71
72 /* ADC injected software start mask */
73 #define CR2_JEXTTRIG_JSWSTRT_Set ((u32)0x00208000)
74 #define CR2_JEXTTRIG_JSWSTRT_Reset ((u32)0xFFDF7FFF)
75
76 /* ADC AWDCH mask */
77 #define CR1_AWDCH_Reset ((u32)0xFFFFFFE0)
78
79 /* ADC SQx mask */
80 #define SQR3_SQ_Set ((u8)0x1F)
81 #define SQR2_SQ_Set ((u8)0x1F)
82 #define SQR1_SQ_Set ((u8)0x1F)
83
84 /* ADC JSQx mask */
85 #define JSQR_JSQ_Set ((u8)0x1F)
86
87 /* ADC JL mask */
88 #define JSQR_JL_Reset ((u32)0xFFCFFFFF)
89
90 /* ADC SMPx mask */
91 #define SMPR1_SMP_Set ((u8)0x07)
92 #define SMPR2_SMP_Set ((u8)0x07)
93
94 /* ADC Analog watchdog enable mode mask */
95 #define CR1_AWDMode_Reset ((u32)0xFF3FFDFF)
96
97 /* ADC TSPD mask */
98 #define CR2_TSVREFE_Set ((u32)0x00800000)
99 #define CR2_TSVREFE_Reset ((u32)0xFF7FFFFF)
100
101 /* ADC JDRx registers= offset */
102 #define JDR_Offset ((u8)0x28)
103
104 /* ADC registers Masks */
105 #define CR1_CLEAR_Mask ((u32)0xFFF0FEFF)
106 #define CR2_CLEAR_Mask ((u32)0xFFF1F7FD)
107 #define SQR1_CLEAR_Mask ((u32)0xFF0FFFFF)
108
109 /* Private macro -------------------------------------------------------------*/
110 /* Private variables ---------------------------------------------------------*/
111 /* Private function prototypes -----------------------------------------------*/
112 /* Private functions ---------------------------------------------------------*/
113
114 /*******************************************************************************
115 * Function Name : ADC_DeInit
116 * Description : Deinitializes the ADCx peripheral registers to their default
117 * reset values.
118 * Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
119 * Output : None
120 * Return : None
121 *******************************************************************************/
122 void ADC_DeInit(ADC_TypeDef* ADCx)
123 {
124 switch (*(u32*)&ADCx)
125 {
126 case ADC1_BASE:
127 /* Enable ADC1 reset state */
128 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
129 /* Release ADC1 from reset state */
130 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
131 break;
132
133 case ADC2_BASE:
134 /* Enable ADC2 reset state */
135 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
136 /* Release ADC2 from reset state */
137 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
138 break;
139
140 default:
141 break;
142 }
143 }
144
145 /*******************************************************************************
146 * Function Name : ADC_Init
147 * Description : Initializes the ADCx peripheral according to the specified parameters
148 * in the ADC_InitStruct.
149 * Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
150 * - ADC_InitStruct: pointer to an ADC_InitTypeDef structure that
151 * contains the configuration information for the specified
152 * ADC peripheral.
153 * Output : None
154 * Return : None
155 ******************************************************************************/
156 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
157 {
158 u32 tmpreg1 = 0;
159 u8 tmpreg2 = 0;
160
161 /* Check the parameters */
162 assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
163 assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
164 assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
165 assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
166 assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
167 assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
168
169 /*---------------------------- ADCx CR1 Configuration -----------------*/
170 /* Get the ADCx CR1 value */
171 tmpreg1 = ADCx->CR1;
172 /* Clear DUALMODE and SCAN bits */
173 tmpreg1 &= CR1_CLEAR_Mask;
174 /* Configure ADCx: Dual mode and scan conversion mode */
175 /* Set DUALMODE bits according to ADC_Mode value */
176 /* Set SCAN bit according to ADC_ScanConvMode value */
177 tmpreg1 |= (u32)(ADC_InitStruct->ADC_Mode | ((u32)ADC_InitStruct->ADC_ScanConvMode << 8));
178 /* Write to ADCx CR1 */
179 ADCx->CR1 = tmpreg1;
180
181 /*---------------------------- ADCx CR2 Configuration -----------------*/
182 /* Get the ADCx CR2 value */
183 tmpreg1 = ADCx->CR2;
184 /* Clear CONT, ALIGN and EXTTRIG bits */
185 tmpreg1 &= CR2_CLEAR_Mask;
186 /* Configure ADCx: external trigger event and continuous conversion mode */
187 /* Set ALIGN bit according to ADC_DataAlign value */
188 /* Set EXTTRIG bits according to ADC_ExternalTrigConv value */
189 /* Set CONT bit according to ADC_ContinuousConvMode value */
190 tmpreg1 |= (u32)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
191 ((u32)ADC_InitStruct->ADC_ContinuousConvMode << 1));
192 /* Write to ADCx CR2 */
193 ADCx->CR2 = tmpreg1;
194
195 /*---------------------------- ADCx SQR1 Configuration -----------------*/
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