📄 stm32f10x_rcc.lst
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679
680 /* Get SYSCLK source -------------------------------------------------------*/
681 tmp = RCC->CFGR & CFGR_SWS_Mask;
682
683 switch (tmp)
684 {
685 case 0x00: /* HSI used as system clock */
686 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
687 break;
688
689 case 0x04: /* HSE used as system clock */
690 RCC_Clocks->SYSCLK_Frequency = HSE_Value;
691 break;
692
693 case 0x08: /* PLL used as system clock */
694 /* Get PLL clock source and multiplication factor ----------------------*/
695 pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
696 pllmull = ( pllmull >> 18) + 2;
697
698 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
699
700 if (pllsource == 0x00)
701 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
702 RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
703 }
704 else
705 {/* HSE selected as PLL clock entry */
706
707 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)
708 {/* HSE oscillator clock divided by 2 */
709
710 RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
711 }
712 else
713 {
714 RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
715 }
716 }
717 break;
718
719 default:
720 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
721 break;
722 }
723
724 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
725 /* Get HCLK prescaler */
726 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
727 tmp = tmp >> 4;
728 presc = APBAHBPrescTable[tmp];
729
730 /* HCLK clock frequency */
731 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
732
733 /* Get PCLK1 prescaler */
734 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
735 tmp = tmp >> 8;
736 presc = APBAHBPrescTable[tmp];
737
738 /* PCLK1 clock frequency */
739 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
740
741 /* Get PCLK2 prescaler */
742 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
743 tmp = tmp >> 11;
744 presc = APBAHBPrescTable[tmp];
745
746 /* PCLK2 clock frequency */
747 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
748
749 /* Get ADCCLK prescaler */
750 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
751 tmp = tmp >> 14;
752 presc = ADCPrescTable[tmp];
753
754 /* ADCCLK clock frequency */
755 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
756 }
757
758 /*******************************************************************************
759 * Function Name : RCC_AHBPeriphClockCmd
760 * Description : Enables or disables the AHB peripheral clock.
761 * Input : - RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
762 * This parameter can be any combination of the following values:
763 * - RCC_AHBPeriph_DMA
764 * - RCC_AHBPeriph_SRAM
765 * - RCC_AHBPeriph_FLITF
766 * SRAM and FLITF clock can be disabled only during sleep mode.
767 * - NewState: new state of the specified peripheral clock.
768 * This parameter can be: ENABLE or DISABLE.
769 * Output : None
770 * Return : None
771 *******************************************************************************/
772 void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState)
773 {
774 /* Check the parameters */
775 assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
776 assert_param(IS_FUNCTIONAL_STATE(NewState));
777
778 if (NewState != DISABLE)
779 {
780 RCC->AHBENR |= RCC_AHBPeriph;
781 }
782 else
783 {
784 RCC->AHBENR &= ~RCC_AHBPeriph;
785 }
786 }
787
788 /*******************************************************************************
789 * Function Name : RCC_APB2PeriphClockCmd
790 * Description : Enables or disables the High Speed APB (APB2) peripheral clock.
791 * Input : - RCC_APB2Periph: specifies the APB2 peripheral to gates its
792 * clock.
793 * This parameter can be any combination of the following values:
794 * - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB
795 * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE
796 * RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1
797 * RCC_APB2Periph_SPI1, RCC_APB2Periph_USART1, RCC_APB2Periph_ALL
798 * - NewState: new state of the specified peripheral clock.
799 * This parameter can be: ENABLE or DISABLE.
800 * Output : None
801 * Return : None
802 *******************************************************************************/
803 void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState)
804 {
805 /* Check the parameters */
806 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
807 assert_param(IS_FUNCTIONAL_STATE(NewState));
808
809 if (NewState != DISABLE)
810 {
811 RCC->APB2ENR |= RCC_APB2Periph;
812 }
813 else
814 {
815 RCC->APB2ENR &= ~RCC_APB2Periph;
816 }
817 }
818
819 /*******************************************************************************
820 * Function Name : RCC_APB1PeriphClockCmd
821 * Description : Enables or disables the Low Speed APB (APB1) peripheral clock.
822 * Input : - RCC_APB1Periph: specifies the APB1 peripheral to gates its
823 * clock.
824 * This parameter can be any combination of the following values:
825 * - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4
826 * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_USART2
827 * RCC_APB1Periph_USART3, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2
828 * RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP
829 * RCC_APB1Periph_PWR, RCC_APB1Periph_ALL
830 * - NewState: new state of the specified peripheral clock.
831 * This parameter can be: ENABLE or DISABLE.
832 * Output : None
833 * Return : None
834 *******************************************************************************/
835 void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState)
836 {
837 /* Check the parameters */
838 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
839 assert_param(IS_FUNCTIONAL_STATE(NewState));
840
841 if (NewState != DISABLE)
842 {
843 RCC->APB1ENR |= RCC_APB1Periph;
844 }
845 else
846 {
847 RCC->APB1ENR &= ~RCC_APB1Periph;
848 }
849 }
850
851 /*******************************************************************************
852 * Function Name : RCC_APB2PeriphResetCmd
853 * Description : Forces or releases High Speed APB (APB2) peripheral reset.
854 * Input : - RCC_APB2Periph: specifies the APB2 peripheral to reset.
855 * This parameter can be any combination of the following values:
856 * - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB
857 * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE
858 * RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1
859 * RCC_APB2Periph_SPI1, RCC_APB2Periph_USART1, RCC_APB2Periph_ALL
860 * - NewState: new state of the specified peripheral reset.
861 * This parameter can be: ENABLE or DISABLE.
862 * Output : None
863 * Return : None
864 *******************************************************************************/
865 void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState)
866 {
867 /* Check the parameters */
868 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
869 assert_param(IS_FUNCTIONAL_STATE(NewState));
870
871 if (NewState != DISABLE)
872 {
873 RCC->APB2RSTR |= RCC_APB2Periph;
874 }
875 else
876 {
877 RCC->APB2RSTR &= ~RCC_APB2Periph;
878 }
879 }
880
881 /*******************************************************************************
882 * Function Name : RCC_APB1PeriphResetCmd
883 * Description : Forces or releases Low Speed APB (APB1) peripheral reset.
884 * Input : - RCC_APB1Periph: specifies the APB1 peripheral to reset.
885 * This parameter can be any combination of the following values:
886 * - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4
887 * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_USART2
888 * RCC_APB1Periph_USART3, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2
889 * RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP
890 * RCC_APB1Periph_PWR, RCC_APB1Periph_ALL
891 * - NewState: new state of the specified peripheral clock.
892 * This parameter can be: ENABLE or DISABLE.
893 * Output : None
894 * Return : None
895 *******************************************************************************/
896 void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState)
897 {
898 /* Check the parameters */
899 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
900 assert_param(IS_FUNCTIONAL_STATE(NewState));
901
902 if (NewState != DISABLE)
903 {
904 RCC->APB1RSTR |= RCC_APB1Periph;
905 }
906 else
907 {
908 RCC->APB1RSTR &= ~RCC_APB1Periph;
909 }
910 }
911
912 /*******************************************************************************
913 * Function Name : RCC_BackupResetCmd
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