📄 stm32f10x_rcc.lst
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209 * - ERROR: HSE oscillator not yet ready
210 *******************************************************************************/
211 ErrorStatus RCC_WaitForHSEStartUp(void)
212 {
213 /* Wait till HSE is ready and if Time out is reached exit */
214 do
215 {
216 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
217 StartUpCounter++;
218 } while((HSEStatus == RESET) && (StartUpCounter != HSEStartUp_TimeOut));
219
220
221 if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
222 {
223 return SUCCESS;
224 }
225 else
226 {
227 return ERROR;
228 }
229 }
230
231 /*******************************************************************************
232 * Function Name : RCC_AdjustHSICalibrationValue
233 * Description : Adjusts the Internal High Speed oscillator (HSI) calibration
234 * value.
235 * Input : - HSICalibrationValue: specifies the calibration trimming value.
236 * This parameter must be a number between 0 and 0x1F.
237 * Output : None
238 * Return : None
239 *******************************************************************************/
240 void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue)
241 {
242 u32 tmpreg = 0;
243
244 /* Check the parameters */
245 assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
246
247 tmpreg = RCC->CR;
248
249 /* Clear HSITRIM[7:3] bits */
250 tmpreg &= CR_HSITRIM_Mask;
251
252 /* Set the HSITRIM[7:3] bits according to HSICalibrationValue value */
253 tmpreg |= (u32)HSICalibrationValue << 3;
254
255 /* Store the new value */
256 RCC->CR = tmpreg;
257 }
258
259 /*******************************************************************************
260 * Function Name : RCC_HSICmd
261 * Description : Enables or disables the Internal High Speed oscillator (HSI).
262 * HSI can not be stopped if it is used directly or through the
263 * PLL as system clock.
264 * Input : - NewState: new state of the HSI.
265 * This parameter can be: ENABLE or DISABLE.
266 * Output : None
267 * Return : None
268 *******************************************************************************/
269 void RCC_HSICmd(FunctionalState NewState)
270 {
271 /* Check the parameters */
272 assert_param(IS_FUNCTIONAL_STATE(NewState));
273
274 *(vu32 *) CR_HSION_BB = (u32)NewState;
275
276 }
277
278 /*******************************************************************************
279 * Function Name : RCC_PLLConfig
280 * Description : Configures the PLL clock source and multiplication factor.
281 * This function must be used only when the PLL is disabled.
282 * Input : - RCC_PLLSource: specifies the PLL entry clock source.
283 * This parameter can be one of the following values:
284 * - RCC_PLLSource_HSI_Div2: HSI oscillator clock divided
285 * by 2 selected as PLL clock entry
286 * - RCC_PLLSource_HSE_Div1: HSE oscillator clock selected
287 * as PLL clock entry
288 * - RCC_PLLSource_HSE_Div2: HSE oscillator clock divided
289 * by 2 selected as PLL clock entry
290 * - RCC_PLLMul: specifies the PLL multiplication factor.
291 * This parameter can be RCC_PLLMul_x where x:[2,16]
292 * Output : None
293 * Return : None
294 *******************************************************************************/
295 void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul)
296 {
297 u32 tmpreg = 0;
298
299 /* Check the parameters */
300 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
301 assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
302
303 tmpreg = RCC->CFGR;
304
305 /* Clear PLLSRC, PLLXTPRE and PLLMUL[21:18] bits */
306 tmpreg &= CFGR_PLL_Mask;
307
308 /* Set the PLL configuration bits */
309 tmpreg |= RCC_PLLSource | RCC_PLLMul;
310
311 /* Store the new value */
312 RCC->CFGR = tmpreg;
313 }
314
315 /*******************************************************************************
316 * Function Name : RCC_PLLCmd
317 * Description : Enables or disables the PLL.
318 * The PLL can not be disabled if it is used as system clock.
319 * Input : - NewState: new state of the PLL.
320 * This parameter can be: ENABLE or DISABLE.
321 * Output : None
322 * Return : None
323 *******************************************************************************/
324 void RCC_PLLCmd(FunctionalState NewState)
325 {
326 /* Check the parameters */
327 assert_param(IS_FUNCTIONAL_STATE(NewState));
328
329 *(vu32 *) CR_PLLON_BB = (u32)NewState;
330 }
331
332 /*******************************************************************************
333 * Function Name : RCC_SYSCLKConfig
334 * Description : Configures the system clock (SYSCLK).
335 * Input : - RCC_SYSCLKSource: specifies the clock source used as system
336 * clock. This parameter can be one of the following values:
337 * - RCC_SYSCLKSource_HSI: HSI selected as system clock
338 * - RCC_SYSCLKSource_HSE: HSE selected as system clock
339 * - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
340 * Output : None
341 * Return : None
342 *******************************************************************************/
343 void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource)
344 {
345 u32 tmpreg = 0;
346
347 /* Check the parameters */
348 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
349
350 tmpreg = RCC->CFGR;
351
352 /* Clear SW[1:0] bits */
353 tmpreg &= CFGR_SW_Mask;
354
355 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
356 tmpreg |= RCC_SYSCLKSource;
357
358 /* Store the new value */
359 RCC->CFGR = tmpreg;
360 }
361
362 /*******************************************************************************
363 * Function Name : RCC_GetSYSCLKSource
364 * Description : Returns the clock source used as system clock.
365 * Input : None
366 * Output : None
367 * Return : The clock source used as system clock. The returned value can
368 * be one of the following:
369 * - 0x00: HSI used as system clock
370 * - 0x04: HSE used as system clock
371 * - 0x08: PLL used as system clock
372 *******************************************************************************/
373 u8 RCC_GetSYSCLKSource(void)
374 {
375 return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
376 }
377
378 /*******************************************************************************
379 * Function Name : RCC_HCLKConfig
380 * Description : Configures the AHB clock (HCLK).
381 * Input : - RCC_HCLK: defines the AHB clock. This clock is derived
382 * from the system clock (SYSCLK).
383 * This parameter can be one of the following values:
384 * - RCC_SYSCLK_Div1: AHB clock = SYSCLK
385 * - RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
386 * - RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
387 * - RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
388 * - RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
389 * - RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
390 * - RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
391 * - RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
392 * - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
393 * Output : None
394 * Return : None
395 *******************************************************************************/
396 void RCC_HCLKConfig(u32 RCC_HCLK)
397 {
398 u32 tmpreg = 0;
399
400 /* Check the parameters */
401 assert_param(IS_RCC_HCLK(RCC_HCLK));
402
403 tmpreg = RCC->CFGR;
404
405 /* Clear HPRE[7:4] bits */
406 tmpreg &= CFGR_HPRE_Reset_Mask;
407
408 /* Set HPRE[7:4] bits according to RCC_HCLK value */
409 tmpreg |= RCC_HCLK;
410
411 /* Store the new value */
412 RCC->CFGR = tmpreg;
413 }
414
415 /*******************************************************************************
416 * Function Name : RCC_PCLK1Config
417 * Description : Configures the Low Speed APB clock (PCLK1).
418 * Input : - RCC_PCLK1: defines the APB1 clock. This clock is derived
419 * from the AHB clock (HCLK).
420 * This parameter can be one of the following values:
421 * - RCC_HCLK_Div1: APB1 clock = HCLK
422 * - RCC_HCLK_Div2: APB1 clock = HCLK/2
423 * - RCC_HCLK_Div4: APB1 clock = HCLK/4
424 * - RCC_HCLK_Div8: APB1 clock = HCLK/8
425 * - RCC_HCLK_Div16: APB1 clock = HCLK/16
426 * Output : None
427 * Return : None
428 *******************************************************************************/
429 void RCC_PCLK1Config(u32 RCC_PCLK1)
430 {
431 u32 tmpreg = 0;
432
433 /* Check the parameters */
434 assert_param(IS_RCC_PCLK(RCC_PCLK1));
435
436 tmpreg = RCC->CFGR;
437
438 /* Clear PPRE1[10:8] bits */
439 tmpreg &= CFGR_PPRE1_Reset_Mask;
440
441 /* Set PPRE1[10:8] bits according to RCC_PCLK1 value */
442 tmpreg |= RCC_PCLK1;
443
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