stm32f10x_tim1.lst

完成数据的采集

    412          
    413            /* Set the Ouput Compare Mode */
    414            tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8;
    415          
    416            TIM1->CCMR1 = (u16)tmpccmr;
    417          
    418            /* Set the Output State */
    419            *(vu32 *) CCER_CC2E_BB = TIM1_OCInitStruct->TIM1_OutputState;
    420          
    421            /* Set the Output N State */
    422            *(vu32 *) CCER_CC2NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
    423          
    424            /* Set the Output Polarity */
    425            *(vu32 *) CCER_CC2P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
    426          
    427            /* Set the Output N Polarity */
    428            *(vu32 *) CCER_CC2NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
    429          
    430            /* Set the Output Idle state */
    431            *(vu32 *) CR2_OIS2_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
    432          
    433            /* Set the Output N Idle state */
    434            *(vu32 *) CR2_OIS2N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
    435          
    436            /* Set the Pulse value */
    437            TIM1->CCR2 = TIM1_OCInitStruct->TIM1_Pulse;
    438          }
    439          
    440          /*******************************************************************************
    441          * Function Name  : TIM1_OC3Init
    442          * Description    : Initializes the TIM1 Channel3 according to the specified
    443          *                  parameters in the TIM1_OCInitStruct.
    444          * Input          : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
    445          *                    contains the configuration information for the TIM1 peripheral.
    446          * Output         : None
    447          * Return         : None
    448          *******************************************************************************/
    449          void TIM1_OC3Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
    450          {
    451            u16 tmpccmr = 0;
    452          
    453            /* Check the parameters */
    454            assert_param(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
    455            assert_param(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
    456            assert_param(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));
    457            assert_param(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
    458            assert_param(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
    459            assert_param(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
    460            assert_param(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));
    461          
    462            tmpccmr = TIM1->CCMR2;
    463          
    464            /* Disable the Channel 3: Reset the CCE Bit */
    465            *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset;
    466          
    467            /* Reset the Output Compare Bits */
    468             tmpccmr &= OC13Mode_Mask;
    469          
    470            /* Set the Ouput Compare Mode */
    471            tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode;
    472          
    473            TIM1->CCMR2 = tmpccmr;
    474          
    475            /* Set the Output State */
    476            *(vu32 *) CCER_CC3E_BB = TIM1_OCInitStruct->TIM1_OutputState;
    477          
    478            /* Set the Output N State */
    479            *(vu32 *) CCER_CC3NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
    480          
    481            /* Set the Output Polarity */
    482            *(vu32 *) CCER_CC3P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
    483          
    484            /* Set the Output N Polarity */
    485            *(vu32 *) CCER_CC3NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
    486          
    487            /* Set the Output Idle state */
    488            *(vu32 *) CR2_OIS3_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
    489          
    490            /* Set the Output N Idle state */
    491            *(vu32 *) CR2_OIS3N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
    492          
    493            /* Set the Pulse value */
    494            TIM1->CCR3 = TIM1_OCInitStruct->TIM1_Pulse;
    495          }
    496          
    497          /*******************************************************************************
    498          * Function Name  : TIM1_OC4Init
    499          * Description    : Initializes the TIM1 Channel4 according to the specified
    500          *                  parameters in the TIM1_OCInitStruct.
    501          * Input          : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
    502          *                    contains the configuration information for the TIM1 peripheral.
    503          * Output         : None
    504          * Return         : None
    505          *******************************************************************************/
    506          void TIM1_OC4Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
    507          {
    508            u32 tmpccmr = 0;
    509          
    510            /* Check the parameters */
    511            assert_param(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
    512            assert_param(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
    513            assert_param(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
    514            assert_param(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
    515          
    516            tmpccmr = TIM1->CCMR2;
    517          
    518            /* Disable the Channel 4: Reset the CCE Bit */
    519            *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset;
    520          
    521            /* Reset the Output Compare Bits */
    522             tmpccmr &= OC24Mode_Mask;
    523          
    524            /* Set the Ouput Compare Mode */
    525            tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8;
    526          
    527            TIM1->CCMR2 = (u16)tmpccmr;
    528          
    529            /* Set the Output State */
    530            *(vu32 *) CCER_CC4E_BB = TIM1_OCInitStruct->TIM1_OutputState;
    531          
    532            /* Set the Output Polarity */
    533            *(vu32 *) CCER_CC4P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
    534          
    535            /* Set the Output Idle state */
    536            *(vu32 *) CR2_OIS4_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
    537          
    538            /* Set the Pulse value */
    539            TIM1->CCR4 = TIM1_OCInitStruct->TIM1_Pulse;
    540          }
    541          
    542          /*******************************************************************************
    543          * Function Name  : TIM1_BDTRConfig
    544          * Description    : Configures the: Break feature, dead time, Lock level, the OSSI,
    545          *                  the OSSR State and the AOE(automatic output enable).
    546          * Input          : - TIM1_BDTRInitStruct: pointer to a TIM1_BDTRInitTypeDef
    547          *                    structure that contains the BDTR Register configuration
    548          *                    information for the TIM1 peripheral.
    549          * Output         : None
    550          * Return         : None
    551          *******************************************************************************/
    552          void TIM1_BDTRConfig(TIM1_BDTRInitTypeDef *TIM1_BDTRInitStruct)
    553          {
    554            u16 tmpbdtr = 0;
    555          
    556            /* Check the parameters */
    557            assert_param(IS_TIM1_OSSR_STATE(TIM1_BDTRInitStruct->TIM1_OSSRState));
    558            assert_param(IS_TIM1_OSSI_STATE(TIM1_BDTRInitStruct->TIM1_OSSIState));
    559            assert_param(IS_TIM1_LOCK_LEVEL(TIM1_BDTRInitStruct->TIM1_LOCKLevel));
    560            assert_param(IS_TIM1_BREAK_STATE(TIM1_BDTRInitStruct->TIM1_Break));
    561            assert_param(IS_TIM1_BREAK_POLARITY(TIM1_BDTRInitStruct->TIM1_BreakPolarity));
    562            assert_param(IS_TIM1_AUTOMATIC_OUTPUT_STATE(TIM1_BDTRInitStruct->TIM1_AutomaticOutput));
    563          
    564            tmpbdtr = TIM1->BDTR;
    565          
    566            /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
    567               the OSSI State, the dead time value and the Automatic Output Enable Bit */
    568          
    569            tmpbdtr = (u32)TIM1_BDTRInitStruct->TIM1_OSSRState | TIM1_BDTRInitStruct->TIM1_OSSIState |
    570                       TIM1_BDTRInitStruct->TIM1_LOCKLevel | TIM1_BDTRInitStruct->TIM1_DeadTime |
    571          			 TIM1_BDTRInitStruct->TIM1_Break | TIM1_BDTRInitStruct->TIM1_BreakPolarity |
    572                       TIM1_BDTRInitStruct->TIM1_AutomaticOutput;
    573          
    574            TIM1->BDTR = tmpbdtr;
    575          }
    576          
    577          /*******************************************************************************
    578          * Function Name  : TIM1_ICInit
    579          * Description    : Initializes the TIM1 peripheral according to the specified
    580          *                  parameters in the TIM1_ICInitStruct.
    581          * Input          : - TIM1_ICInitStruct: pointer to a TIM1_ICInitTypeDef structure
    582          *                    that contains the configuration information for the specified
    583          *                    TIM1 peripheral.
    584          * Output         : None
    585          * Return         : None
    586          *******************************************************************************/
    587          void TIM1_ICInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct)
    588          {
    589            /* Check the parameters */
    590            assert_param(IS_TIM1_CHANNEL(TIM1_ICInitStruct->TIM1_Channel));
    591            assert_param(IS_TIM1_IC_POLARITY(TIM1_ICInitStruct->TIM1_ICPolarity));
    592            assert_param(IS_TIM1_IC_SELECTION(TIM1_ICInitStruct->TIM1_ICSelection));
    593            assert_param(IS_TIM1_IC_PRESCALER(TIM1_ICInitStruct->TIM1_ICPrescaler));
    594            assert_param(IS_TIM1_IC_FILTER(TIM1_ICInitStruct->TIM1_ICFilter));
    595          
    596            if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_1)
    597            {
    598              /* TI1 Configuration */
    599              TI1_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
    600                         TIM1_ICInitStruct->TIM1_ICSelection,
    601                         TIM1_ICInitStruct->TIM1_ICFilter);
    602          
    603              /* Set the Input Capture Prescaler value */
    604              TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
    605            }
    606            else if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_2)
    607            {
    608              /* TI2 Configuration */
    609              TI2_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
    610                         TIM1_ICInitStruct->TIM1_ICSelection,
    611                         TIM1_ICInitStruct->TIM1_ICFilter);
    612          
    613              /* Set the Input Capture Prescaler value */
    614              TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
    615            }
    616            else if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_3)
    617            {
    618              /* TI3 Configuration */
    619              TI3_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
    620                         TIM1_ICInitStruct->TIM1_ICSelection,
    621                         TIM1_ICInitStruct->TIM1_ICFilter);
    622          
    623              /* Set the Input Capture Prescaler value */
    624              TIM1_SetIC3Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
    625            }
    626            else
    627            {
    628              /* TI4 Configuration */
    629              TI4_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
    630                         TIM1_ICInitStruct->TIM1_ICSelection,