📄 stm32f10x_tim1.lst
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193 #define OC2PE_BitNumber 0x0B
194 #define CCMR1_OC2PE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2PE_BitNumber * 4))
195
196 /* Alias word address of OC2CE bit */
197 #define OC2CE_BitNumber 0x0F
198 #define CCMR1_OC2CE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2CE_BitNumber * 4))
199
200 /* --- TIM1 CCMR2 Register ---- */
201 /* Alias word address of OC3FE bit */
202 #define CCMR2_OFFSET (TIM1_OFFSET + 0x1C)
203 #define OC3FE_BitNumber 0x02
204 #define CCMR2_OC3FE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3FE_BitNumber * 4))
205
206 /* Alias word address of OC3PE bit */
207 #define OC3PE_BitNumber 0x03
208 #define CCMR2_OC3PE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3PE_BitNumber * 4))
209
210 /* Alias word address of OC3CE bit */
211 #define OC3CE_BitNumber 0x07
212 #define CCMR2_OC3CE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3CE_BitNumber * 4))
213
214 /* Alias word address of OC4FE bit */
215 #define OC4FE_BitNumber 0x0A
216 #define CCMR2_OC4FE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4FE_BitNumber * 4))
217
218 /* Alias word address of OC4PE bit */
219 #define OC4PE_BitNumber 0x0B
220 #define CCMR2_OC4PE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4PE_BitNumber * 4))
221
222 /* Alias word address of OC4CE bit */
223 #define OC4CE_BitNumber 0x0F
224 #define CCMR2_OC4CE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4CE_BitNumber * 4))
225
226 /* --------------------- TIM1 registers bit mask ------------------------- */
227 /* TIM1 CR1 Mask */
228 #define CR1_CounterMode_Mask ((u16)0x039F)
229 #define CR1_CKD_Mask ((u16)0x00FF)
230
231 /* TIM1 CR2 Mask */
232 #define CR2_MMS_Mask ((u16)0x0080)
233
234 /* TIM1 SMCR Mask */
235 #define SMCR_SMS_Mask ((u16)0xFFF0)
236 #define SMCR_ETR_Mask ((u16)0x40F7)
237 #define SMCR_TS_Mask ((u16)0xFF87)
238 #define SMCR_ECE_Set ((u16)0x0001)
239
240 /* TIM1 CCMRx Mask */
241 #define CCMR_CC13S_Mask ((u16)0xFFFC)
242 #define CCMR_CC24S_Mask ((u16)0xFCFF)
243 #define CCMR_TI13Direct_Set ((u16)0x0001)
244 #define CCMR_TI24Direct_Set ((u16)0x0100)
245 #define CCMR_OCM13_Mask ((u16)0x7F0F)
246 #define CCMR_OCM24_Mask ((u16)0x0F7F)
247 #define CCMR_IC13PSC_Mask ((u16)0xFFF3)
248 #define CCMR_IC24PSC_Mask ((u16)0xF3FF)
249 #define CCMR_IC13F_Mask ((u16)0xFF0F)
250 #define CCMR_IC24F_Mask ((u16)0x0FFF)
251 #define OC13Mode_Mask ((u16)0xFF00)
252 #define OC24Mode_Mask ((u16)0x00FF)
253
254 /* TIM1 CCER Set/Reset Bit */
255 #define CCER_CCE_Set ((u16)0x0001)
256 #define CCER_CCE_Reset ((u16)0x0000)
257
258 /* TIM1 DMA Mask */
259 #define DCR_DMA_Mask ((u16)0x0000)
260
261 /* TIM1 private Masks */
262 #define TIM1_Period_Reset_Mask ((u16)0xFFFF)
263 #define TIM1_Prescaler_Reset_Mask ((u16)0x0000)
264 #define TIM1_RepetitionCounter_Reset_Mask ((u16)0x0000)
265 #define TIM1_Pulse_Reset_Mask ((u16)0x0000)
266 #define TIM1_ICFilter_Mask ((u8)0x00)
267 #define TIM1_DeadTime_Reset_Mask ((u16)0x0000)
268
269 /* Private macro -------------------------------------------------------------*/
270 /* Private variables ---------------------------------------------------------*/
271 /* Private function prototypes -----------------------------------------------*/
272 static void TI1_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
273 u8 TIM1_ICFilter);
274 static void TI2_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
275 u8 TIM1_ICFilter);
276 static void TI3_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
277 u8 TIM1_ICFilter);
278 static void TI4_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
279 u8 TIM1_ICFilter);
280
281 /*******************************************************************************
282 * Function Name : TIM1_DeInit
283 * Description : Deinitializes the TIM1 peripheral registers to their default
284 * reset values.
285 * Input : None
286 * Output : None
287 * Return : None
288 *******************************************************************************/
289 void TIM1_DeInit(void)
290 {
291 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
292 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
293 }
294
295 /*******************************************************************************
296 * Function Name : TIM1_TimeBaseInit
297 * Description : Initializes the TIM1 Time Base Unit according to the specified
298 * parameters in the TIM1_TimeBaseInitStruct.
299 * Input : - TIM1_TimeBaseInitStruct: pointer to a TIM1_TimeBaseInitTypeDef
300 * structure that contains the configuration information for
301 * the specified TIM1 peripheral.
302 * Output : None
303 * Return : None
304 *******************************************************************************/
305 void TIM1_TimeBaseInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct)
306 {
307 /* Check the parameters */
308 assert_param(IS_TIM1_COUNTER_MODE(TIM1_TimeBaseInitStruct->TIM1_CounterMode));
309 assert_param(IS_TIM1_CKD_DIV(TIM1_TimeBaseInitStruct->TIM1_ClockDivision));
310
311 /* Set the Autoreload value */
312 TIM1->ARR = TIM1_TimeBaseInitStruct->TIM1_Period ;
313
314 /* Set the Prescaler value */
315 TIM1->PSC = TIM1_TimeBaseInitStruct->TIM1_Prescaler;
316
317 /* Select the Counter Mode and set the clock division */
318 TIM1->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
319 TIM1->CR1 |= (u32)TIM1_TimeBaseInitStruct->TIM1_ClockDivision |
320 TIM1_TimeBaseInitStruct->TIM1_CounterMode;
321
322 /* Set the Repetition Counter value */
323 TIM1->RCR = TIM1_TimeBaseInitStruct->TIM1_RepetitionCounter;
324 }
325
326 /*******************************************************************************
327 * Function Name : TIM1_OC1Init
328 * Description : Initializes the TIM1 Channel1 according to the specified
329 * parameters in the TIM1_OCInitStruct.
330 * Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
331 * contains the configuration information for the TIM1 peripheral.
332 * Output : None
333 * Return : None
334 *******************************************************************************/
335 void TIM1_OC1Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
336 {
337 u16 tmpccmr = 0;
338
339 /* Check the parameters */
340 assert_param(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
341 assert_param(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
342 assert_param(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));
343 assert_param(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
344 assert_param(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
345 assert_param(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
346 assert_param(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));
347
348 tmpccmr = TIM1->CCMR1;
349
350 /* Disable the Channel 1: Reset the CCE Bit */
351 *(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset;
352
353 /* Reset the Output Compare Bits */
354 tmpccmr &= OC13Mode_Mask;
355
356 /* Set the Ouput Compare Mode */
357 tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode;
358
359 TIM1->CCMR1 = tmpccmr;
360
361 /* Set the Output State */
362 *(vu32 *) CCER_CC1E_BB = TIM1_OCInitStruct->TIM1_OutputState;
363
364 /* Set the Output N State */
365 *(vu32 *) CCER_CC1NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
366
367 /* Set the Output Polarity */
368 *(vu32 *) CCER_CC1P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
369
370 /* Set the Output N Polarity */
371 *(vu32 *) CCER_CC1NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
372
373 /* Set the Output Idle state */
374 *(vu32 *) CR2_OIS1_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
375
376 /* Set the Output N Idle state */
377 *(vu32 *) CR2_OIS1N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
378
379 /* Set the Pulse value */
380 TIM1->CCR1 = TIM1_OCInitStruct->TIM1_Pulse;
381 }
382
383 /*******************************************************************************
384 * Function Name : TIM1_OC2Init
385 * Description : Initializes the TIM1 Channel2 according to the specified
386 * parameters in the TIM1_OCInitStruct.
387 * Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
388 * contains the configuration information for the TIM1 peripheral.
389 * Output : None
390 * Return : None
391 *******************************************************************************/
392 void TIM1_OC2Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
393 {
394 u32 tmpccmr = 0;
395
396 /* Check the parameters */
397 assert_param(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
398 assert_param(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
399 assert_param(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));
400 assert_param(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
401 assert_param(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
402 assert_param(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
403 assert_param(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));
404
405 tmpccmr = TIM1->CCMR1;
406
407 /* Disable the Channel 2: Reset the CCE Bit */
408 *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset;
409
410 /* Reset the Output Compare Bits */
411 tmpccmr &= OC24Mode_Mask;
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