stm32f10x_tim1.lst

完成数据的采集

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#                                                       30/Jul/2008  11:02:20 #
# IAR ARM ANSI C/C++ Compiler V5.11.0.20622/W32 EVALUATION                    #
# Copyright 1999-2007 IAR Systems. All rights reserved.                       #
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#    Cpu mode     =  thumb                                                    #
#    Endian       =  little                                                   #
#    Source file  =  E:\library\src\stm32f10x_tim1.c                          #
#    Command line =  E:\library\src\stm32f10x_tim1.c -D EMB_FLASH -lcN        #
#                    E:\ELE\yten\pro\Release\List\ -o                         #
#                    E:\ELE\yten\pro\Release\Obj\ --no_cse --no_unroll        #
#                    --no_inline --no_code_motion --no_tbaa --no_clustering   #
#                    --no_scheduling --debug --endian little --cpu Cortex-M3  #
#                    -e --fpu None --dlib_config "C:\Program Files\IAR        #
#                    Systems\Embedded Workbench 5.0                           #
#                    Evaluation\ARM\INC\DLib_Config_Normal.h" -I              #
#                    E:\ELE\yten\pro\ -I E:\ELE\yten\pro\..\LIBRARY\INC\ -I   #
#                    "C:\Program Files\IAR Systems\Embedded Workbench 5.0     #
#                    Evaluation\ARM\INC\" -On                                 #
#    List file    =  E:\ELE\yten\pro\Release\List\stm32f10x_tim1.lst          #
#    Object file  =  E:\ELE\yten\pro\Release\Obj\stm32f10x_tim1.o             #
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E:\library\src\stm32f10x_tim1.c
      1          /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
      2          * File Name          : stm32f10x_tim1.c
      3          * Author             : MCD Application Team
      4          * Version            : V1.0
      5          * Date               : 10/08/2007
      6          * Description        : This file provides all the TIM1 software functions.
      7          ********************************************************************************
      8          * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
      9          * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
     10          * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
     11          * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
     12          * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
     13          * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
     14          *******************************************************************************/
     15          
     16          /* Includes ------------------------------------------------------------------*/
     17          #include "stm32f10x_tim1.h"
     18          #include "stm32f10x_rcc.h"
     19          
     20          /* Private typedef -----------------------------------------------------------*/
     21          /* Private define ------------------------------------------------------------*/
     22          
     23          /* ------------ TIM1 registers bit address in the alias region ----------- */
     24          #define TIM1_OFFSET    (TIM1_BASE - PERIPH_BASE)
     25          
     26          /* --- TIM1 CR1 Register ---*/
     27          /* Alias word address of CEN bit */
     28          #define CR1_OFFSET        (TIM1_OFFSET + 0x00)
     29          #define CEN_BitNumber     0x00
     30          #define CR1_CEN_BB        (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (CEN_BitNumber * 4))
     31          
     32          /* Alias word address of UDIS bit */
     33          #define UDIS_BitNumber    0x01
     34          #define CR1_UDIS_BB       (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (UDIS_BitNumber * 4))
     35          
     36          /* Alias word address of URS bit */
     37          #define URS_BitNumber     0x02
     38          #define CR1_URS_BB        (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (URS_BitNumber * 4))
     39          
     40          /* Alias word address of OPM bit */
     41          #define OPM_BitNumber     0x03
     42          #define CR1_OPM_BB        (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (OPM_BitNumber * 4))
     43          
     44          /* Alias word address of ARPE bit */
     45          #define ARPE_BitNumber    0x07
     46          #define CR1_ARPE_BB       (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (ARPE_BitNumber * 4))
     47          
     48          /* --- TIM1 CR2 Register --- */
     49          /* Alias word address of CCPC bit */
     50          #define CR2_OFFSET        (TIM1_OFFSET + 0x04)
     51          #define CCPC_BitNumber    0x00
     52          #define CR2_CCPC_BB       (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCPC_BitNumber * 4))
     53          
     54          /* Alias word address of CCUS bit */
     55          #define CCUS_BitNumber    0x02
     56          #define CR2_CCUS_BB       (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCUS_BitNumber * 4))
     57          
     58          /* Alias word address of CCDS bit */
     59          #define CCDS_BitNumber    0x03
     60          #define CR2_CCDS_BB       (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCDS_BitNumber * 4))
     61          
     62          /* Alias word address of TI1S bit */
     63          #define TI1S_BitNumber    0x07
     64          #define CR2_TI1S_BB       (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (TI1S_BitNumber * 4))
     65          
     66          /* Alias word address of OIS1 bit */
     67          #define OIS1_BitNumber    0x08
     68          #define CR2_OIS1_BB       (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS1_BitNumber * 4))
     69          
     70          /* Alias word address of OIS1N bit */
     71          #define OIS1N_BitNumber   0x09
     72          #define CR2_OIS1N_BB      (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS1N_BitNumber * 4))
     73          
     74          /* Alias word address of OIS2 bit */
     75          #define OIS2_BitNumber    0x0A
     76          #define CR2_OIS2_BB      (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS2_BitNumber * 4))
     77          
     78          /* Alias word address of OIS2N bit */
     79          #define OIS2N_BitNumber   0x0B
     80          #define CR2_OIS2N_BB      (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS2N_BitNumber * 4))
     81          
     82          /* Alias word address of OIS3 bit */
     83          #define OIS3_BitNumber    0x0C
     84          #define CR2_OIS3_BB       (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS3_BitNumber * 4))
     85          
     86          /* Alias word address of OIS3N bit */
     87          #define OIS3N_BitNumber   0x0D
     88          #define CR2_OIS3N_BB      (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS3N_BitNumber * 4))
     89          
     90          /* Alias word address of OIS4 bit */
     91          #define OIS4_BitNumber    0x0E
     92          #define CR2_OIS4_BB       (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS4_BitNumber * 4))
     93          
     94          /* --- TIM1 SMCR Register --- */
     95          /* Alias word address of MSM bit */
     96          #define SMCR_OFFSET       (TIM1_OFFSET + 0x08)
     97          #define MSM_BitNumber     0x07
     98          #define SMCR_MSM_BB       (PERIPH_BB_BASE + (SMCR_OFFSET * 32) + (MSM_BitNumber * 4))
     99          
    100          /* Alias word address of ECE bit */
    101          #define ECE_BitNumber     0x0E
    102          #define SMCR_ECE_BB       (PERIPH_BB_BASE + (SMCR_OFFSET * 32) + (ECE_BitNumber * 4))
    103          
    104          /* --- TIM1 EGR Register --- */
    105          /* Alias word address of UG bit */
    106          #define EGR_OFFSET        (TIM1_OFFSET + 0x14)
    107          #define UG_BitNumber      0x00
    108          #define EGR_UG_BB         (PERIPH_BB_BASE + (EGR_OFFSET * 32) + (UG_BitNumber * 4))
    109          
    110          /* --- TIM1 CCER Register --- */
    111          /* Alias word address of CC1E bit */
    112          #define CCER_OFFSET       (TIM1_OFFSET + 0x20)
    113          #define CC1E_BitNumber    0x00
    114          #define CCER_CC1E_BB      (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1E_BitNumber * 4))
    115          
    116          /* Alias word address of CC1P bit */
    117          #define CC1P_BitNumber    0x01
    118          #define CCER_CC1P_BB      (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1P_BitNumber * 4))
    119          
    120          /* Alias word address of CC1NE bit */
    121          #define CC1NE_BitNumber   0x02
    122          #define CCER_CC1NE_BB     (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1NE_BitNumber * 4))
    123          
    124          /* Alias word address of CC1NP bit */
    125          #define CC1NP_BitNumber   0x03
    126          #define CCER_CC1NP_BB     (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1NP_BitNumber * 4))
    127          
    128          /* Alias word address of CC2E bit */
    129          #define CC2E_BitNumber    0x04
    130          #define CCER_CC2E_BB      (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2E_BitNumber * 4))
    131          
    132          /* Alias word address of CC2P bit */
    133          #define CC2P_BitNumber    0x05
    134          #define CCER_CC2P_BB      (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2P_BitNumber * 4))
    135          
    136          /* Alias word address of CC2NE bit */
    137          #define CC2NE_BitNumber   0x06
    138          #define CCER_CC2NE_BB     (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2NE_BitNumber * 4))
    139          
    140          /* Alias word address of CC2NP bit */
    141          #define CC2NP_BitNumber   0x07
    142          #define CCER_CC2NP_BB     (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2NP_BitNumber * 4))
    143          
    144          /* Alias word address of CC3E bit */
    145          #define CC3E_BitNumber    0x08
    146          #define CCER_CC3E_BB      (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3E_BitNumber * 4))
    147          
    148          /* Alias word address of CC3P bit */
    149          #define CC3P_BitNumber    0x09
    150          #define CCER_CC3P_BB      (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3P_BitNumber * 4))
    151          
    152          /* Alias word address of CC3NE bit */
    153          #define CC3NE_BitNumber   0x0A
    154          #define CCER_CC3NE_BB     (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3NE_BitNumber * 4))
    155          
    156          /* Alias word address of CC3NP bit */
    157          #define CC3NP_BitNumber   0x0B
    158          #define CCER_CC3NP_BB     (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3NP_BitNumber * 4))
    159          
    160          /* Alias word address of CC4E bit */
    161          #define CC4E_BitNumber    0x0C
    162          #define CCER_CC4E_BB      (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC4E_BitNumber * 4))
    163          
    164          /* Alias word address of CC4P bit */
    165          #define CC4P_BitNumber    0x0D
    166          #define CCER_CC4P_BB      (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC4P_BitNumber * 4))
    167          
    168          /* --- TIM1 BDTR Register --- */
    169          /* Alias word address of MOE bit */
    170          #define BDTR_OFFSET       (TIM1_OFFSET + 0x44)
    171          #define MOE_BitNumber     0x0F
    172          #define BDTR_MOE_BB       (PERIPH_BB_BASE + (BDTR_OFFSET * 32) + (MOE_BitNumber * 4))
    173          
    174          /* --- TIM1 CCMR1 Register --- */
    175          /* Alias word address of OC1FE bit */
    176          #define CCMR1_OFFSET      (TIM1_OFFSET + 0x18)
    177          #define OC1FE_BitNumber   0x02
    178          #define CCMR1_OC1FE_BB    (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1FE_BitNumber * 4))
    179          
    180          /* Alias word address of OC1PE bit */
    181          #define OC1PE_BitNumber   0x03
    182          #define CCMR1_OC1PE_BB    (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1PE_BitNumber * 4))
    183          
    184          /* Alias word address of OC1CE bit */
    185          #define OC1CE_BitNumber   0x07
    186          #define CCMR1_OC1CE_BB    (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1CE_BitNumber * 4))
    187          
    188          /* Alias word address of OC2FE bit */
    189          #define OC2FE_BitNumber   0x0A
    190          #define CCMR1_OC2FE_BB    (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2FE_BitNumber * 4))
    191          
    192          /* Alias word address of OC2PE bit */