📄 stm32f10x_dma.lst
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###############################################################################
# #
# 30/Jul/2008 11:02:23 #
# IAR ARM ANSI C/C++ Compiler V5.11.0.20622/W32 EVALUATION #
# Copyright 1999-2007 IAR Systems. All rights reserved. #
# #
# Cpu mode = thumb #
# Endian = little #
# Source file = E:\library\src\stm32f10x_dma.c #
# Command line = E:\library\src\stm32f10x_dma.c -D EMB_FLASH -lcN #
# E:\ELE\yten\pro\Release\List\ -o #
# E:\ELE\yten\pro\Release\Obj\ --no_cse --no_unroll #
# --no_inline --no_code_motion --no_tbaa --no_clustering #
# --no_scheduling --debug --endian little --cpu Cortex-M3 #
# -e --fpu None --dlib_config "C:\Program Files\IAR #
# Systems\Embedded Workbench 5.0 #
# Evaluation\ARM\INC\DLib_Config_Normal.h" -I #
# E:\ELE\yten\pro\ -I E:\ELE\yten\pro\..\LIBRARY\INC\ -I #
# "C:\Program Files\IAR Systems\Embedded Workbench 5.0 #
# Evaluation\ARM\INC\" -On #
# List file = E:\ELE\yten\pro\Release\List\stm32f10x_dma.lst #
# Object file = E:\ELE\yten\pro\Release\Obj\stm32f10x_dma.o #
# #
# #
###############################################################################
E:\library\src\stm32f10x_dma.c
1 /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
2 * File Name : stm32f10x_dma.c
3 * Author : MCD Application Team
4 * Version : V1.0
5 * Date : 10/08/2007
6 * Description : This file provides all the DMA firmware functions.
7 ********************************************************************************
8 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
9 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
10 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
11 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
12 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
13 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
14 *******************************************************************************/
15
16 /* Includes ------------------------------------------------------------------*/
17 #include "stm32f10x_dma.h"
18 #include "stm32f10x_rcc.h"
19
20 /* Private typedef -----------------------------------------------------------*/
21 /* Private define ------------------------------------------------------------*/
22 /* DMA ENABLE mask */
23 #define CCR_ENABLE_Set ((u32)0x00000001)
24 #define CCR_ENABLE_Reset ((u32)0xFFFFFFFE)
25
26 /* DMA Channelx interrupt pending bit masks */
27 #define DMA_Channel1_IT_Mask ((u32)0x0000000F)
28 #define DMA_Channel2_IT_Mask ((u32)0x000000F0)
29 #define DMA_Channel3_IT_Mask ((u32)0x00000F00)
30 #define DMA_Channel4_IT_Mask ((u32)0x0000F000)
31 #define DMA_Channel5_IT_Mask ((u32)0x000F0000)
32 #define DMA_Channel6_IT_Mask ((u32)0x00F00000)
33 #define DMA_Channel7_IT_Mask ((u32)0x0F000000)
34
35 /* DMA registers Masks */
36 #define CCR_CLEAR_Mask ((u32)0xFFFF800F)
37
38 /* Private macro -------------------------------------------------------------*/
39 /* Private variables ---------------------------------------------------------*/
40 /* Private function prototypes -----------------------------------------------*/
41 /* Private functions ---------------------------------------------------------*/
42
43 /*******************************************************************************
44 * Function Name : DMA_DeInit
45 * Description : Deinitializes the DMA Channelx registers to their default reset
46 * values.
47 * Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
48 * Channel.
49 * Output : None
50 * Return : None
51 *******************************************************************************/
52 void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx)
53 {
54 /* DMA Channelx disable */
55 DMA_Cmd(DMA_Channelx, DISABLE);
56
57 /* Reset Channelx control register */
58 DMA_Channelx->CCR = 0;
59
60 /* Reset Channelx remaining bytes register */
61 DMA_Channelx->CNDTR = 0;
62
63 /* Reset Channelx peripheral address register */
64 DMA_Channelx->CPAR = 0;
65
66 /* Reset Channelx memory address register */
67 DMA_Channelx->CMAR = 0;
68
69 switch (*(u32*)&DMA_Channelx)
70 {
71 case DMA_Channel1_BASE:
72 /* Reset interrupt pending bits for Channel1 */
73 DMA->IFCR |= DMA_Channel1_IT_Mask;
74 break;
75
76 case DMA_Channel2_BASE:
77 /* Reset interrupt pending bits for Channel2 */
78 DMA->IFCR |= DMA_Channel2_IT_Mask;
79 break;
80
81 case DMA_Channel3_BASE:
82 /* Reset interrupt pending bits for Channel3 */
83 DMA->IFCR |= DMA_Channel3_IT_Mask;
84 break;
85
86 case DMA_Channel4_BASE:
87 /* Reset interrupt pending bits for Channel4 */
88 DMA->IFCR |= DMA_Channel4_IT_Mask;
89 break;
90
91 case DMA_Channel5_BASE:
92 /* Reset interrupt pending bits for Channel5 */
93 DMA->IFCR |= DMA_Channel5_IT_Mask;
94 break;
95
96 case DMA_Channel6_BASE:
97 /* Reset interrupt pending bits for Channel6 */
98 DMA->IFCR |= DMA_Channel6_IT_Mask;
99 break;
100
101 case DMA_Channel7_BASE:
102 /* Reset interrupt pending bits for Channel7 */
103 DMA->IFCR |= DMA_Channel7_IT_Mask;
104 break;
105
106 default:
107 break;
108 }
109 }
110
111 /*******************************************************************************
112 * Function Name : DMA_Init
113 * Description : Initializes the DMA Channelx according to the specified
114 * parameters in the DMA_InitStruct.
115 * Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
116 * Channel.
117 * - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
118 * contains the configuration information for the specified
119 * DMA Channel.
120 * Output : None
121 * Return : None
122 ******************************************************************************/
123 void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct)
124 {
125 u32 tmpreg = 0;
126
127 /* Check the parameters */
128 assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
129 assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
130 assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
131 assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
132 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
133 assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
134 assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
135 assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
136 assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
137
138 /*--------------------------- DMA Channelx CCR Configuration -----------------*/
139 /* Get the DMA_Channelx CCR value */
140 tmpreg = DMA_Channelx->CCR;
141 /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRCULAR and DIR bits */
142 tmpreg &= CCR_CLEAR_Mask;
143 /* Configure DMA Channelx: data transfer, data size, priority level and mode */
144 /* Set DIR bit according to DMA_DIR value */
145 /* Set CIRCULAR bit according to DMA_Mode value */
146 /* Set PINC bit according to DMA_PeripheralInc value */
147 /* Set MINC bit according to DMA_MemoryInc value */
148 /* Set PSIZE bits according to DMA_PeripheralDataSize value */
149 /* Set MSIZE bits according to DMA_MemoryDataSize value */
150 /* Set PL bits according to DMA_Priority value */
151 /* Set the MEM2MEM bit according to DMA_M2M value */
152 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
153 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
154 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
155 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
156 /* Write to DMA Channelx CCR */
157 DMA_Channelx->CCR = tmpreg;
158
159 /*--------------------------- DMA Channelx CNBTR Configuration ---------------*/
160 /* Write to DMA Channelx CNBTR */
161 DMA_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
162
163 /*--------------------------- DMA Channelx CPAR Configuration ----------------*/
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