freq_measure.vhd

来自「用CPLD对输入脉冲进行计数」· VHDL 代码 · 共 37 行

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

library ieee;
use ieee.std_logic_1164.all;
library altera;
use altera.altera_syn_attributes.all;

entity freq_measure is
	port
	(
		cat_choice : out std_logic_vector(5 downto 0);
		clk : in std_logic;
		freq_in : in std_logic;
		rst : in std_logic;
		segout : out std_logic_vector(6 downto 0)
	);

end freq_measure;

architecture ppl_type of freq_measure is

begin

end;