prev_cmp_part5.tan.qmsg

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

{ "Info" "ITDB_TH_RESULT" "myram:Ram\|altsyncram:altsyncram_component\|altsyncram_3os1:auto_generated\|ram_block1a0~porta_address_reg1 Address\[1\] CLK -3.356 ns memory " "Info: th for memory \"myram:Ram\|altsyncram:altsyncram_component\|altsyncram_3os1:auto_generated\|ram_block1a0~porta_address_reg1\" (data pin = \"Address\[1\]\", clock pin = \"CLK\") is -3.356 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.707 ns + Longest memory " "Info: + Longest clock path from clock \"CLK\" to destination memory is 2.707 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 2; CLK Node = 'CLK'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns CLK~clkctrl 2 COMB CLKCTRL_G2 51 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 51; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.934 ns) + CELL(0.661 ns) 2.707 ns myram:Ram\|altsyncram:altsyncram_component\|altsyncram_3os1:auto_generated\|ram_block1a0~porta_address_reg1 3 MEM M4K_X13_Y10 0 " "Info: 3: + IC(0.934 ns) + CELL(0.661 ns) = 2.707 ns; Loc. = M4K_X13_Y10; Fanout = 0; MEM Node = 'myram:Ram\|altsyncram:altsyncram_component\|altsyncram_3os1:auto_generated\|ram_block1a0~porta_address_reg1'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.595 ns" { CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } } { "db/altsyncram_3os1.tdf" "" { Text "C:/altera/72sp2/LAB8/part5/db/altsyncram_3os1.tdf" 37 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 61.32 % ) " "Info: Total cell delay = 1.660 ns ( 61.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.047 ns ( 38.68 % ) " "Info: Total interconnect delay = 1.047 ns ( 38.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.707 ns" { CLK CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "2.707 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~porta_address_reg1 {} } { 0.000ns 0.000ns 0.113ns 0.934ns } { 0.000ns 0.999ns 0.000ns 0.661ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.234 ns + " "Info: + Micro hold delay of destination is 0.234 ns" {  } { { "db/altsyncram_3os1.tdf" "" { Text "C:/altera/72sp2/LAB8/part5/db/altsyncram_3os1.tdf" 37 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.297 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 6.297 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.820 ns) 0.820 ns Address\[1\] 1 PIN PIN_AA11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.820 ns) = 0.820 ns; Loc. = PIN_AA11; Fanout = 1; PIN Node = 'Address\[1\]'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Address[1] } "NODE_NAME" } } { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.335 ns) + CELL(0.142 ns) 6.297 ns myram:Ram\|altsyncram:altsyncram_component\|altsyncram_3os1:auto_generated\|ram_block1a0~porta_address_reg1 2 MEM M4K_X13_Y10 0 " "Info: 2: + IC(5.335 ns) + CELL(0.142 ns) = 6.297 ns; Loc. = M4K_X13_Y10; Fanout = 0; MEM Node = 'myram:Ram\|altsyncram:altsyncram_component\|altsyncram_3os1:auto_generated\|ram_block1a0~porta_address_reg1'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.477 ns" { Address[1] myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } } { "db/altsyncram_3os1.tdf" "" { Text "C:/altera/72sp2/LAB8/part5/db/altsyncram_3os1.tdf" 37 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.962 ns ( 15.28 % ) " "Info: Total cell delay = 0.962 ns ( 15.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.335 ns ( 84.72 % ) " "Info: Total interconnect delay = 5.335 ns ( 84.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.297 ns" { Address[1] myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "6.297 ns" { Address[1] {} Address[1]~combout {} myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~porta_address_reg1 {} } { 0.000ns 0.000ns 5.335ns } { 0.000ns 0.820ns 0.142ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.707 ns" { CLK CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "2.707 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~porta_address_reg1 {} } { 0.000ns 0.000ns 0.113ns 0.934ns } { 0.000ns 0.999ns 0.000ns 0.661ns } "" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.297 ns" { Address[1] myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "6.297 ns" { Address[1] {} Address[1]~combout {} myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~porta_address_reg1 {} } { 0.000ns 0.000ns 5.335ns } { 0.000ns 0.820ns 0.142ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "118 " "Info: Allocated 118 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 12 14:30:20 2008 " "Info: Processing ended: Mon May 12 14:30:20 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}