prev_cmp_part5.tan.qmsg

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 2 -1 0 } } { "c:/altera/72sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "Clock " "Info: Detected ripple clock \"Clock\" as buffer" {  } { { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 12 -1 0 } } { "c:/altera/72sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "Clock" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register count:Cnt\|y.01000 memory myram:Ram\|altsyncram:altsyncram_component\|altsyncram_3os1:auto_generated\|ram_block1a0~portb_address_reg1 123.14 MHz 8.121 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 123.14 MHz between source register \"count:Cnt\|y.01000\" and destination memory \"myram:Ram\|altsyncram:altsyncram_component\|altsyncram_3os1:auto_generated\|ram_block1a0~portb_address_reg1\" (period= 8.121 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.564 ns + Longest register memory " "Info: + Longest register to memory delay is 3.564 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count:Cnt\|y.01000 1 REG LCFF_X7_Y10_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X7_Y10_N7; Fanout = 3; REG Node = 'count:Cnt\|y.01000'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { count:Cnt|y.01000 } "NODE_NAME" } } { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.306 ns) + CELL(0.398 ns) 1.704 ns count:Cnt\|WideOr3~95 2 COMB LCCOMB_X7_Y10_N16 3 " "Info: 2: + IC(1.306 ns) + CELL(0.398 ns) = 1.704 ns; Loc. = LCCOMB_X7_Y10_N16; Fanout = 3; COMB Node = 'count:Cnt\|WideOr3~95'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.704 ns" { count:Cnt|y.01000 count:Cnt|WideOr3~95 } "NODE_NAME" } } { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.281 ns) + CELL(0.437 ns) 2.422 ns count:Cnt\|WideOr3~98 3 COMB LCCOMB_X7_Y10_N22 8 " "Info: 3: + IC(0.281 ns) + CELL(0.437 ns) = 2.422 ns; Loc. = LCCOMB_X7_Y10_N22; Fanout = 8; COMB Node = 'count:Cnt\|WideOr3~98'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.718 ns" { count:Cnt|WideOr3~95 count:Cnt|WideOr3~98 } "NODE_NAME" } } { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.142 ns) 3.564 ns myram:Ram\|altsyncram:altsyncram_component\|altsyncram_3os1:auto_generated\|ram_block1a0~portb_address_reg1 4 MEM M4K_X13_Y10 8 " "Info: 4: + IC(1.000 ns) + CELL(0.142 ns) = 3.564 ns; Loc. = M4K_X13_Y10; Fanout = 8; MEM Node = 'myram:Ram\|altsyncram:altsyncram_component\|altsyncram_3os1:auto_generated\|ram_block1a0~portb_address_reg1'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.142 ns" { count:Cnt|WideOr3~98 myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~portb_address_reg1 } "NODE_NAME" } } { "db/altsyncram_3os1.tdf" "" { Text "C:/altera/72sp2/LAB8/part5/db/altsyncram_3os1.tdf" 37 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.977 ns ( 27.41 % ) " "Info: Total cell delay = 0.977 ns ( 27.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.587 ns ( 72.59 % ) " "Info: Total interconnect delay = 2.587 ns ( 72.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.564 ns" { count:Cnt|y.01000 count:Cnt|WideOr3~95 count:Cnt|WideOr3~98 myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~portb_address_reg1 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "3.564 ns" { count:Cnt|y.01000 {} count:Cnt|WideOr3~95 {} count:Cnt|WideOr3~98 {} myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~portb_address_reg1 {} } { 0.000ns 1.306ns 0.281ns 1.000ns } { 0.000ns 0.398ns 0.437ns 0.142ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.272 ns - Smallest " "Info: - Smallest clock skew is -4.272 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.735 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLK\" to destination memory is 2.735 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 2; CLK Node = 'CLK'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns CLK~clkctrl 2 COMB CLKCTRL_G2 51 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 51; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.934 ns) + CELL(0.689 ns) 2.735 ns myram:Ram\|altsyncram:altsyncram_component\|altsyncram_3os1:auto_generated\|ram_block1a0~portb_address_reg1 3 MEM M4K_X13_Y10 8 " "Info: 3: + IC(0.934 ns) + CELL(0.689 ns) = 2.735 ns; Loc. = M4K_X13_Y10; Fanout = 8; MEM Node = 'myram:Ram\|altsyncram:altsyncram_component\|altsyncram_3os1:auto_generated\|ram_block1a0~portb_address_reg1'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.623 ns" { CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~portb_address_reg1 } "NODE_NAME" } } { "db/altsyncram_3os1.tdf" "" { Text "C:/altera/72sp2/LAB8/part5/db/altsyncram_3os1.tdf" 37 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.688 ns ( 61.72 % ) " "Info: Total cell delay = 1.688 ns ( 61.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.047 ns ( 38.28 % ) " "Info: Total interconnect delay = 1.047 ns ( 38.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.735 ns" { CLK CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~portb_address_reg1 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "2.735 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~portb_address_reg1 {} } { 0.000ns 0.000ns 0.113ns 0.934ns } { 0.000ns 0.999ns 0.000ns 0.689ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.007 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 7.007 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 2; CLK Node = 'CLK'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.731 ns) + CELL(0.787 ns) 3.517 ns Clock 2 REG LCFF_X28_Y11_N11 2 " "Info: 2: + IC(1.731 ns) + CELL(0.787 ns) = 3.517 ns; Loc. = LCFF_X28_Y11_N11; Fanout = 2; REG Node = 'Clock'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { CLK Clock } "NODE_NAME" } } { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.951 ns) + CELL(0.000 ns) 5.468 ns Clock~clkctrl 3 COMB CLKCTRL_G12 32 " "Info: 3: + IC(1.951 ns) + CELL(0.000 ns) = 5.468 ns; Loc. = CLKCTRL_G12; Fanout = 32; COMB Node = 'Clock~clkctrl'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.951 ns" { Clock Clock~clkctrl } "NODE_NAME" } } { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.002 ns) + CELL(0.537 ns) 7.007 ns count:Cnt\|y.01000 4 REG LCFF_X7_Y10_N7 3 " "Info: 4: + IC(1.002 ns) + CELL(0.537 ns) = 7.007 ns; Loc. = LCFF_X7_Y10_N7; Fanout = 3; REG Node = 'count:Cnt\|y.01000'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.539 ns" { Clock~clkctrl count:Cnt|y.01000 } "NODE_NAME" } } { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 33.15 % ) " "Info: Total cell delay = 2.323 ns ( 33.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.684 ns ( 66.85 % ) " "Info: Total interconnect delay = 4.684 ns ( 66.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.007 ns" { CLK Clock Clock~clkctrl count:Cnt|y.01000 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "7.007 ns" { CLK {} CLK~combout {} Clock {} Clock~clkctrl {} count:Cnt|y.01000 {} } { 0.000ns 0.000ns 1.731ns 1.951ns 1.002ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.735 ns" { CLK CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~portb_address_reg1 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "2.735 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~portb_address_reg1 {} } { 0.000ns 0.000ns 0.113ns 0.934ns } { 0.000ns 0.999ns 0.000ns 0.689ns } "" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.007 ns" { CLK Clock Clock~clkctrl count:Cnt|y.01000 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "7.007 ns" { CLK {} CLK~combout {} Clock {} Clock~clkctrl {} count:Cnt|y.01000 {} } { 0.000ns 0.000ns 1.731ns 1.951ns 1.002ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 68 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.035 ns + " "Info: + Micro setup delay of destination is 0.035 ns" {  } { { "db/altsyncram_3os1.tdf" "" { Text "C:/altera/72sp2/LAB8/part5/db/altsyncram_3os1.tdf" 37 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.564 ns" { count:Cnt|y.01000 count:Cnt|WideOr3~95 count:Cnt|WideOr3~98 myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~portb_address_reg1 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "3.564 ns" { count:Cnt|y.01000 {} count:Cnt|WideOr3~95 {} count:Cnt|WideOr3~98 {} myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~portb_address_reg1 {} } { 0.000ns 1.306ns 0.281ns 1.000ns } { 0.000ns 0.398ns 0.437ns 0.142ns } "" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.735 ns" { CLK CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~portb_address_reg1 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "2.735 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~portb_address_reg1 {} } { 0.000ns 0.000ns 0.113ns 0.934ns } { 0.000ns 0.999ns 0.000ns 0.689ns } "" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.007 ns" { CLK Clock Clock~clkctrl count:Cnt|y.01000 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "7.007 ns" { CLK {} CLK~combout {} Clock {} Clock~clkctrl {} count:Cnt|y.01000 {} } { 0.000ns 0.000ns 1.731ns 1.951ns 1.002ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}