📄 prev_cmp_part5.map.qmsg
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 part5.v(23) " "Warning (10230): Verilog HDL assignment warning at part5.v(23): truncated value with size 32 to match size of target (1)" { } { { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 23 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "count count:Cnt " "Info: Elaborating entity \"count\" for hierarchy \"count:Cnt\"" { } { { "part5.v" "Cnt" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 29 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "myram myram:Ram " "Info: Elaborating entity \"myram\" for hierarchy \"myram:Ram\"" { } { { "part5.v" "Ram" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 30 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" { } { { "altsyncram.tdf" "" { Text "c:/altera/72sp2/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram myram:Ram\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"myram:Ram\|altsyncram:altsyncram_component\"" { } { { "part5.v" "altsyncram_component" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 128 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "myram:Ram\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"myram:Ram\|altsyncram:altsyncram_component\"" { } { { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 128 0 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_3os1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3os1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_3os1 " "Info: Found entity 1: altsyncram_3os1" { } { { "db/altsyncram_3os1.tdf" "" { Text "C:/altera/72sp2/LAB8/part5/db/altsyncram_3os1.tdf" 27 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_3os1 myram:Ram\|altsyncram:altsyncram_component\|altsyncram_3os1:auto_generated " "Info: Elaborating entity \"altsyncram_3os1\" for hierarchy \"myram:Ram\|altsyncram:altsyncram_component\|altsyncram_3os1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/72sp2/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "display display:D1 " "Info: Elaborating entity \"display\" for hierarchy \"display:D1\"" { } { { "part5.v" "D1" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 34 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|part5\|count:Cnt\|y 32 " "Info: State machine \"\|part5\|count:Cnt\|y\" contains 32 states" { } { { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 68 -1 0 } } } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
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