prev_cmp_part5.map.qmsg

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Web Edition " "Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 12 14:29:32 2008 " "Info: Processing started: Mon May 12 14:29:32 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "cnt Cnt part5.v(13) " "Info (10281): Verilog HDL Declaration information at part5.v(13): object \"cnt\" differs only in case from object \"Cnt\" in the same scope" {  } { { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 13 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "y Y part5.v(68) " "Info (10281): Verilog HDL Declaration information at part5.v(68): object \"y\" differs only in case from object \"Y\" in the same scope" {  } { { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 68 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part5.v 4 4 " "Info: Found 4 design units, including 4 entities, in source file part5.v" { { "Info" "ISGN_ENTITY_NAME" "1 part5 " "Info: Found entity 1: part5" {  } { { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 count " "Info: Found entity 2: count" {  } { { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 64 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "3 myram " "Info: Found entity 3: myram" {  } { { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 93 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "4 display " "Info: Found entity 4: display" {  } { { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 156 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "part5 " "Info: Elaborating entity \"part5\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 part5.v(17) " "Warning (10230): Verilog HDL assignment warning at part5.v(17): truncated value with size 32 to match size of target (3)" {  } { { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 part5.v(18) " "Warning (10230): Verilog HDL assignment warning at part5.v(18): truncated value with size 32 to match size of target (11)" {  } { { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 18 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 part5.v(20) " "Warning (10230): Verilog HDL assignment warning at part5.v(20): truncated value with size 32 to match size of target (11)" {  } { { "part5.v" "" { Text "C:/altera/72sp2/LAB8/part5/part5.v" 20 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}