📄 part5_v.sdo
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// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
// Device: Altera EP2C35F672C6 Package FBGA672
//
//
// This SDF file should be used for PrimeTime (Verilog) only
//
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "part5")
(DATE "05/21/2008 10:42:52")
(VENDOR "Altera")
(PROGRAM "Quartus II")
(VERSION "Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Web Edition")
(DIVIDER .)
(TIMESCALE 1 ps)
(CELL
(CELLTYPE "cycloneii_memory_register")
(INSTANCE Ram\|altsyncram_component\|auto_generated\|ram_block1a0.ram_portadatain_reg)
(DELAY
(ABSOLUTE
(PORT data[0] (6702:6702:6702) (6702:6702:6702))
(PORT data[1] (6749:6749:6749) (6749:6749:6749))
(PORT data[2] (6729:6729:6729) (6729:6729:6729))
(PORT data[3] (7180:7180:7180) (7180:7180:7180))
(PORT data[4] (7146:7146:7146) (7146:7146:7146))
(PORT data[5] (7045:7045:7045) (7045:7045:7045))
(PORT data[6] (7174:7174:7174) (7174:7174:7174))
(PORT data[7] (6791:6791:6791) (6791:6791:6791))
(PORT clk (1606:1606:1606) (1606:1606:1606))
(IOPATH (posedge clk) dataout[0] (209:209:209) (209:209:209))
(IOPATH (posedge clk) dataout[1] (209:209:209) (209:209:209))
(IOPATH (posedge clk) dataout[2] (209:209:209) (209:209:209))
(IOPATH (posedge clk) dataout[3] (209:209:209) (209:209:209))
(IOPATH (posedge clk) dataout[4] (209:209:209) (209:209:209))
(IOPATH (posedge clk) dataout[5] (209:209:209) (209:209:209))
(IOPATH (posedge clk) dataout[6] (209:209:209) (209:209:209))
(IOPATH (posedge clk) dataout[7] (209:209:209) (209:209:209))
)
)
(TIMINGCHECK
(SETUPHOLD data[0] (posedge clk) (35:35:35) (234:234:234))
(SETUPHOLD data[1] (posedge clk) (35:35:35) (234:234:234))
(SETUPHOLD data[2] (posedge clk) (35:35:35) (234:234:234))
(SETUPHOLD data[3] (posedge clk) (35:35:35) (234:234:234))
(SETUPHOLD data[4] (posedge clk) (35:35:35) (234:234:234))
(SETUPHOLD data[5] (posedge clk) (35:35:35) (234:234:234))
(SETUPHOLD data[6] (posedge clk) (35:35:35) (234:234:234))
(SETUPHOLD data[7] (posedge clk) (35:35:35) (234:234:234))
)
)
(CELL
(CELLTYPE "cycloneii_memory_addr_register")
(INSTANCE Ram\|altsyncram_component\|auto_generated\|ram_block1a0.ram_portaaddr_reg)
(DELAY
(ABSOLUTE
(PORT address[0] (6975:6975:6975) (6975:6975:6975))
(PORT address[1] (7244:7244:7244) (7244:7244:7244))
(PORT address[2] (7447:7447:7447) (7447:7447:7447))
(PORT address[3] (6532:6532:6532) (6532:6532:6532))
(PORT address[4] (6974:6974:6974) (6974:6974:6974))
(PORT clk (1607:1607:1607) (1607:1607:1607))
(IOPATH (posedge clk) dataout[0] (209:209:209) (209:209:209))
(IOPATH (posedge clk) dataout[1] (209:209:209) (209:209:209))
(IOPATH (posedge clk) dataout[2] (209:209:209) (209:209:209))
(IOPATH (posedge clk) dataout[3] (209:209:209) (209:209:209))
(IOPATH (posedge clk) dataout[4] (209:209:209) (209:209:209))
)
)
(TIMINGCHECK
(SETUPHOLD address[0] (posedge clk) (35:35:35) (234:234:234))
(SETUPHOLD address[1] (posedge clk) (35:35:35) (234:234:234))
(SETUPHOLD address[2] (posedge clk) (35:35:35) (234:234:234))
(SETUPHOLD address[3] (posedge clk) (35:35:35) (234:234:234))
(SETUPHOLD address[4] (posedge clk) (35:35:35) (234:234:234))
)
)
(CELL
(CELLTYPE "dffe")
(INSTANCE Ram\|altsyncram_component\|auto_generated\|ram_block1a0.ram_portawe_reg)
(DELAY
(ABSOLUTE
(PORT D (7410:7410:7410) (7410:7410:7410))
(PORT CLK (1607:1607:1607) (1607:1607:1607))
(IOPATH (posedge CLK) Q (209:209:209) (209:209:209))
)
)
(TIMINGCHECK
(SETUPHOLD D (posedge CLK) (35:35:35) (234:234:234))
)
)
(CELL
(CELLTYPE "cycloneii_memory_addr_register")
(INSTANCE Ram\|altsyncram_component\|auto_generated\|ram_block1a0.ram_portbaddr_reg)
(DELAY
(ABSOLUTE
(PORT address[0] (1135:1135:1135) (1135:1135:1135))
(PORT address[1] (927:927:927) (927:927:927))
(PORT address[2] (1160:1160:1160) (1160:1160:1160))
(PORT address[3] (996:996:996) (996:996:996))
(PORT address[4] (926:926:926) (926:926:926))
(PORT clk (1635:1635:1635) (1635:1635:1635))
(IOPATH (posedge clk) dataout[0] (209:209:209) (209:209:209))
(IOPATH (posedge clk) dataout[1] (209:209:209) (209:209:209))
(IOPATH (posedge clk) dataout[2] (209:209:209) (209:209:209))
(IOPATH (posedge clk) dataout[3] (209:209:209) (209:209:209))
(IOPATH (posedge clk) dataout[4] (209:209:209) (209:209:209))
)
)
(TIMINGCHECK
(SETUPHOLD address[0] (posedge clk) (35:35:35) (234:234:234))
(SETUPHOLD address[1] (posedge clk) (35:35:35) (234:234:234))
(SETUPHOLD address[2] (posedge clk) (35:35:35) (234:234:234))
(SETUPHOLD address[3] (posedge clk) (35:35:35) (234:234:234))
(SETUPHOLD address[4] (posedge clk) (35:35:35) (234:234:234))
)
)
(CELL
(CELLTYPE "dffe")
(INSTANCE Ram\|altsyncram_component\|auto_generated\|ram_block1a0.ram_portbrewe_reg)
(DELAY
(ABSOLUTE
(PORT D (312:312:312) (312:312:312))
(PORT CLK (1635:1635:1635) (1635:1635:1635))
(IOPATH (posedge CLK) Q (209:209:209) (209:209:209))
)
)
(TIMINGCHECK
(SETUPHOLD D (posedge CLK) (35:35:35) (234:234:234))
)
)
(CELL
(CELLTYPE "cycloneii_ram_internal")
(INSTANCE Ram\|altsyncram_component\|auto_generated\|ram_block1a0.internal_ram)
(DELAY
(ABSOLUTE
(IOPATH portawriteenable portadataout[0] (2993:2993:2993) (2993:2993:2993))
(IOPATH portadatain[0] portadataout[0] (2993:2993:2993) (2993:2993:2993))
(IOPATH t_portaaddress_portadataout_in_join portadataout[0] (2993:2993:2993) (2993:2993:2993))
(IOPATH portawriteenable portadataout[1] (2993:2993:2993) (2993:2993:2993))
(IOPATH portadatain[1] portadataout[1] (2993:2993:2993) (2993:2993:2993))
(IOPATH t_portaaddress_portadataout_in_join portadataout[1] (2993:2993:2993) (2993:2993:2993))
(IOPATH portawriteenable portadataout[2] (2993:2993:2993) (2993:2993:2993))
(IOPATH portadatain[2] portadataout[2] (2993:2993:2993) (2993:2993:2993))
(IOPATH t_portaaddress_portadataout_in_join portadataout[2] (2993:2993:2993) (2993:2993:2993))
(IOPATH portawriteenable portadataout[3] (2993:2993:2993) (2993:2993:2993))
(IOPATH portadatain[3] portadataout[3] (2993:2993:2993) (2993:2993:2993))
(IOPATH t_portaaddress_portadataout_in_join portadataout[3] (2993:2993:2993) (2993:2993:2993))
(IOPATH portawriteenable portadataout[4] (2993:2993:2993) (2993:2993:2993))
(IOPATH portadatain[4] portadataout[4] (2993:2993:2993) (2993:2993:2993))
(IOPATH t_portaaddress_portadataout_in_join portadataout[4] (2993:2993:2993) (2993:2993:2993))
(IOPATH portawriteenable portadataout[5] (2993:2993:2993) (2993:2993:2993))
(IOPATH portadatain[5] portadataout[5] (2993:2993:2993) (2993:2993:2993))
(IOPATH t_portaaddress_portadataout_in_join portadataout[5] (2993:2993:2993) (2993:2993:2993))
(IOPATH portawriteenable portadataout[6] (2993:2993:2993) (2993:2993:2993))
(IOPATH portadatain[6] portadataout[6] (2993:2993:2993) (2993:2993:2993))
(IOPATH t_portaaddress_portadataout_in_join portadataout[6] (2993:2993:2993) (2993:2993:2993))
(IOPATH portawriteenable portadataout[7] (2993:2993:2993) (2993:2993:2993))
(IOPATH portadatain[7] portadataout[7] (2993:2993:2993) (2993:2993:2993))
(IOPATH t_portaaddress_portadataout_in_join portadataout[7] (2993:2993:2993) (2993:2993:2993))
(IOPATH portbrewe portbdataout[0] (2991:2991:2991) (2991:2991:2991))
(IOPATH t_portbaddress_portbdataout_in_join portbdataout[0] (2991:2991:2991) (2991:2991:2991))
(IOPATH portbrewe portbdataout[1] (2991:2991:2991) (2991:2991:2991))
(IOPATH t_portbaddress_portbdataout_in_join portbdataout[1] (2991:2991:2991) (2991:2991:2991))
(IOPATH portbrewe portbdataout[2] (2991:2991:2991) (2991:2991:2991))
(IOPATH t_portbaddress_portbdataout_in_join portbdataout[2] (2991:2991:2991) (2991:2991:2991))
(IOPATH portbrewe portbdataout[3] (2991:2991:2991) (2991:2991:2991))
(IOPATH t_portbaddress_portbdataout_in_join portbdataout[3] (2991:2991:2991) (2991:2991:2991))
(IOPATH portbrewe portbdataout[4] (2991:2991:2991) (2991:2991:2991))
(IOPATH t_portbaddress_portbdataout_in_join portbdataout[4] (2991:2991:2991) (2991:2991:2991))
(IOPATH portbrewe portbdataout[5] (2991:2991:2991) (2991:2991:2991))
(IOPATH t_portbaddress_portbdataout_in_join portbdataout[5] (2991:2991:2991) (2991:2991:2991))
(IOPATH portbrewe portbdataout[6] (2991:2991:2991) (2991:2991:2991))
(IOPATH t_portbaddress_portbdataout_in_join portbdataout[6] (2991:2991:2991) (2991:2991:2991))
(IOPATH portbrewe portbdataout[7] (2991:2991:2991) (2991:2991:2991))
(IOPATH t_portbaddress_portbdataout_in_join portbdataout[7] (2991:2991:2991) (2991:2991:2991))
)
)
)
(CELL
(CELLTYPE "cycloneii_lcell_comb")
(INSTANCE Add2\~132)
(DELAY
(ABSOLUTE
(PORT datab (496:496:496) (496:496:496))
(IOPATH datab combout (420:420:420) (420:420:420))
(IOPATH datab cout (393:393:393) (393:393:393))
(IOPATH datad combout (150:150:150) (150:150:150))
)
)
)
(CELL
(CELLTYPE "cycloneii_lcell_comb")
(INSTANCE Add2\~134)
(DELAY
(ABSOLUTE
(PORT datab (483:483:483) (483:483:483))
(IOPATH datab combout (420:420:420) (420:420:420))
(IOPATH datab cout (393:393:393) (393:393:393))
(IOPATH datad combout (150:150:150) (150:150:150))
(IOPATH cin combout (410:410:410) (410:410:410))
(IOPATH cin cout (71:71:71) (71:71:71))
)
)
)
(CELL
(CELLTYPE "cycloneii_lcell_comb")
(INSTANCE Add2\~136)
(DELAY
(ABSOLUTE
(PORT datab (491:491:491) (491:491:491))
(IOPATH datab combout (420:420:420) (420:420:420))
(IOPATH datab cout (393:393:393) (393:393:393))
(IOPATH datad combout (150:150:150) (150:150:150))
(IOPATH cin combout (410:410:410) (410:410:410))
(IOPATH cin cout (71:71:71) (71:71:71))
)
)
)
(CELL
(CELLTYPE "cycloneii_lcell_comb")
(INSTANCE Add2\~138)
(DELAY
(ABSOLUTE
(PORT dataa (498:498:498) (498:498:498))
(IOPATH dataa combout (438:438:438) (438:438:438))
(IOPATH dataa cout (414:414:414) (414:414:414))
(IOPATH datad combout (150:150:150) (150:150:150))
(IOPATH cin combout (410:410:410) (410:410:410))
(IOPATH cin cout (71:71:71) (71:71:71))
)
)
)
(CELL
(CELLTYPE "cycloneii_lcell_comb")
(INSTANCE Add2\~140)
(DELAY
(ABSOLUTE
(PORT datab (490:490:490) (490:490:490))
(IOPATH datab combout (420:420:420) (420:420:420))
(IOPATH datab cout (393:393:393) (393:393:393))
(IOPATH datad combout (150:150:150) (150:150:150))
(IOPATH cin combout (410:410:410) (410:410:410))
(IOPATH cin cout (71:71:71) (71:71:71))
)
)
)
(CELL
(CELLTYPE "cycloneii_lcell_comb")
(INSTANCE Add2\~142)
(DELAY
(ABSOLUTE
(PORT datab (484:484:484) (484:484:484))
(IOPATH datab combout (420:420:420) (420:420:420))
(IOPATH datab cout (393:393:393) (393:393:393))
(IOPATH datad combout (150:150:150) (150:150:150))
(IOPATH cin combout (410:410:410) (410:410:410))
(IOPATH cin cout (71:71:71) (71:71:71))
)
)
)
(CELL
(CELLTYPE "cycloneii_lcell_comb")
(INSTANCE Add2\~144)
(DELAY
(ABSOLUTE
(PORT dataa (504:504:504) (504:504:504))
(IOPATH dataa combout (438:438:438) (438:438:438))
(IOPATH dataa cout (504:504:504) (504:504:504))
(IOPATH datad combout (150:150:150) (150:150:150))
(IOPATH cin combout (410:410:410) (410:410:410))
(IOPATH cin cout (159:159:159) (159:159:159))
)
)
)
(CELL
(CELLTYPE "cycloneii_lcell_comb")
(INSTANCE Add2\~146)
(DELAY
(ABSOLUTE
(PORT dataa (464:464:464) (464:464:464))
(IOPATH dataa combout (438:438:438) (438:438:438))
(IOPATH dataa cout (414:414:414) (414:414:414))
(IOPATH datad combout (150:150:150) (150:150:150))
(IOPATH cin combout (410:410:410) (410:410:410))
(IOPATH cin cout (71:71:71) (71:71:71))
)
)
)
(CELL
(CELLTYPE "cycloneii_lcell_comb")
(INSTANCE Add2\~148)
(DELAY
(ABSOLUTE
(PORT datab (310:310:310) (310:310:310))
(IOPATH datab combout (420:420:420) (420:420:420))
(IOPATH datab cout (393:393:393) (393:393:393))
(IOPATH datad combout (150:150:150) (150:150:150))
(IOPATH cin combout (410:410:410) (410:410:410))
(IOPATH cin cout (71:71:71) (71:71:71))
)
)
)
(CELL
(CELLTYPE "cycloneii_lcell_comb")
(INSTANCE Add2\~150)
(DELAY
(ABSOLUTE
(PORT dataa (325:325:325) (325:325:325))
(IOPATH dataa combout (438:438:438) (438:438:438))
(IOPATH dataa cout (414:414:414) (414:414:414))
(IOPATH datad combout (150:150:150) (150:150:150))
(IOPATH cin combout (410:410:410) (410:410:410))
(IOPATH cin cout (71:71:71) (71:71:71))
)
)
)
(CELL
(CELLTYPE "cycloneii_lcell_comb")
(INSTANCE Add2\~152)
(DELAY
(ABSOLUTE
(PORT datad (445:445:445) (445:445:445))
(IOPATH datad combout (150:150:150) (150:150:150))
(IOPATH cin combout (410:410:410) (410:410:410))
)
)
)
(CELL
(CELLTYPE "cycloneii_lcell_comb")
(INSTANCE Add1\~132)
(DELAY
(ABSOLUTE
(PORT datab (319:319:319) (319:319:319))
(IOPATH datab combout (420:420:420) (420:420:420))
(IOPATH datab cout (393:393:393) (393:393:393))
(IOPATH datad combout (150:150:150) (150:150:150))
)
)
)
(CELL
(CELLTYPE "cycloneii_lcell_comb")
(INSTANCE Add1\~134)
(DELAY
(ABSOLUTE
(PORT dataa (325:325:325) (325:325:325))
(IOPATH dataa combout (438:438:438) (438:438:438))
(IOPATH dataa cout (414:414:414) (414:414:414))
(IOPATH datad combout (150:150:150) (150:150:150))
(IOPATH cin combout (410:410:410) (410:410:410))
(IOPATH cin cout (71:71:71) (71:71:71))
)
)
)
(CELL
(CELLTYPE "cycloneii_lcell_comb")
(INSTANCE Add1\~136)
(DELAY
(ABSOLUTE
(PORT datab (483:483:483) (483:483:483))
(IOPATH datab combout (420:420:420) (420:420:420))
(IOPATH datab cout (393:393:393) (393:393:393))
(IOPATH datad combout (150:150:150) (150:150:150))
(IOPATH cin combout (410:410:410) (410:410:410))
(IOPATH cin cout (71:71:71) (71:71:71))
)
)
)
(CELL
(CELLTYPE "cycloneii_lcell_comb")
(INSTANCE Add1\~138)
(DELAY
(ABSOLUTE
(PORT dataa (464:464:464) (464:464:464))
(IOPATH dataa combout (438:438:438) (438:438:438))
(IOPATH dataa cout (504:504:504) (504:504:504))
(IOPATH datad combout (150:150:150) (150:150:150))
(IOPATH cin combout (410:410:410) (410:410:410))
(IOPATH cin cout (159:159:159) (159:159:159))
)
)
)
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