part5.v

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

module part5(CLK, SW_A, Address, Data, Wren, LED, SEG_COM, SEG_DATA);
	input CLK, SW_A, Wren; //SW_A->Reset
	input [4:0] Address;
	input [7:0] Data;
	output LED;
	output [7:0] SEG_COM, SEG_DATA;
	
	wire [3:0] Cnt_v;
	wire [4:0] Count_v;
	wire [7:0] Q, Seg_Count1, Seg_Count2, Seg_Read1, Seg_Read2, Seg_input1, Seg_input2;
	
	reg Clock;
	reg [2:0] cnt;
	reg [10:0] temp1, temp2 ;
	
	always@(posedge CLK) begin
		cnt = cnt+1;
		temp1 = temp1+1;
		if(temp1 == 2000) begin
			temp2 = temp2+1;
			temp1 = 0;
			if(temp2 == 1250) begin
				Clock = Clock+1;
				temp2 = 0;
			end
		end
	end

	count Cnt (Clock, SW_A, Count_v);
	myram Ram (CLK, Data, Count_v, Address, Wren, Q);
	
	assign Cnt_v = {3'b000, Count_v[4]};

	display D1 (Q[3:0],Seg_Read1);
	display D2 (Q[7:4],Seg_Read2);
	display D3 (Data[3:0],Seg_input1);
	display D4 (Data[7:4],Seg_input2);
	display D5 (Count_v[3:0], Seg_Count1);
	display D6 (Cnt_v, Seg_Count2);
	
	assign LED = Wren;
	
	assign SEG_COM = (cnt==0)?8'b01111111:
					 (cnt==1)?8'b10111111:
					 (cnt==2)?8'b11011111:
					 (cnt==3)?8'b11101111:
					 (cnt==4)?8'b11110111:
					 (cnt==5)?8'b11111011:
					 (cnt==6)?8'b11111101:
					 (cnt==7)?8'b11111110:8'b11111111;
					
	assign SEG_DATA = (cnt==0)?Seg_Read1:
					  (cnt==1)?Seg_Read2:
					  (cnt==2)?8'b00000000:
					  (cnt==3)?Seg_input1:
					  (cnt==4)?Seg_input2:
					  (cnt==5)?8'b00000000:
					  (cnt==6)?Seg_Count1:
					  (cnt==7)?Seg_Count2:8'b00000000;

endmodule


module count(CLK, Reset, Q);
	input CLK, Reset;
	output [4:0] Q;
	
	reg [4:0] y, Y;
	
	always@(y) begin
		case(y)
			0:Y=1; 1:Y=2; 2:Y=3; 3:Y=4; 4:Y=5;
			5:Y=6; 6:Y=7; 7:Y=8; 8:Y=9; 9:Y=10;			
			10:Y=11; 11:Y=12; 12:Y=13; 13:Y=14; 14:Y=15;
			15:Y=16; 16:Y=17; 17:Y=18; 18:Y=19; 19:Y=20;			
			20:Y=21; 21:Y=22; 22:Y=23; 23:Y=24; 24:Y=25;
			25:Y=26; 26:Y=27; 27:Y=28; 28:Y=29; 29:Y=30;			
			30:Y=31; 31:Y=0;			
		endcase	
	end
	
	always@(posedge CLK or posedge Reset) begin
		if(Reset == 1)
			y <= 0;
		else
			y <= Y;
	end
	
	assign Q = y;
	
endmodule

module myram (	clock,	data,	rdaddress,	wraddress,	wren,	q);

	input	  clock;
	input	[7:0]  data;
	input	[4:0]  rdaddress;
	input	[4:0]  wraddress;
	input	  wren;
	output	[7:0]  q;

	wire [7:0] sub_wire0;
	wire [7:0] q = sub_wire0[7:0];

	altsyncram	altsyncram_component (
				.wren_a (wren),
				.clock0 (clock),
				.address_a (wraddress),
				.address_b (rdaddress),
				.data_a (data),
				.q_b (sub_wire0),
				.aclr0 (1'b0),
				.aclr1 (1'b0),
				.addressstall_a (1'b0),
				.addressstall_b (1'b0),
				.byteena_a (1'b1),
				.byteena_b (1'b1),
				.clock1 (1'b1),
				.clocken0 (1'b1),
				.clocken1 (1'b1),
				.clocken2 (1'b1),
				.clocken3 (1'b1),
				.data_b ({8{1'b1}}),
				.eccstatus (),
				.q_a (),
				.rden_a (1'b1),
				.rden_b (1'b1),
				.wren_b (1'b0));
	defparam
		altsyncram_component.address_reg_b = "CLOCK0",
		altsyncram_component.clock_enable_input_a = "BYPASS",
		altsyncram_component.clock_enable_input_b = "BYPASS",
		altsyncram_component.clock_enable_output_a = "BYPASS",
		altsyncram_component.clock_enable_output_b = "BYPASS",
		altsyncram_component.init_file = "myram.mif",
		altsyncram_component.intended_device_family = "Cyclone II",
		altsyncram_component.lpm_type = "altsyncram",
		altsyncram_component.numwords_a = 32,
		altsyncram_component.numwords_b = 32,
		altsyncram_component.operation_mode = "DUAL_PORT",
		altsyncram_component.outdata_aclr_b = "NONE",
		altsyncram_component.outdata_reg_b = "UNREGISTERED",
		altsyncram_component.power_up_uninitialized = "FALSE",
		altsyncram_component.ram_block_type = "M4K",
		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
		altsyncram_component.widthad_a = 5,
		altsyncram_component.widthad_b = 5,
		altsyncram_component.width_a = 8,
		altsyncram_component.width_b = 8,
		altsyncram_component.width_byteena_a = 1;


endmodule


module display(in,out);
	input [3:0] in;
	output [7:0] out;
	
	assign out = (in==0)?8'b00111111:
				 (in==1)?8'b00000110:
				 (in==2)?8'b01011011:
				 (in==3)?8'b01001111:
				 (in==4)?8'b01100110:
				 (in==5)?8'b01101101:
				 (in==6)?8'b01111101:
				 (in==7)?8'b00100111:
				 (in==8)?8'b01111111:
				 (in==9)?8'b01101111:
				 (in==10)?8'b01110111:
				 (in==11)?8'b01111100:
				 (in==12)?8'b01011000:
				 (in==13)?8'b01011110:
				 (in==14)?8'b01111011:
				 (in==15)?8'b01110001:8'b00000000;
			
endmodule