part5.vo

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Web Edition"

// DATE "05/21/2008 10:42:52"

// 
// Device: Altera EP2C35F672C6 Package FBGA672
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module part5 (
	CLK,
	SW_A,
	Address,
	Data,
	Wren,
	LED,
	SEG_COM,
	SEG_DATA);
input 	CLK;
input 	SW_A;
input 	[4:0] Address;
input 	[7:0] Data;
input 	Wren;
output 	LED;
output 	[7:0] SEG_COM;
output 	[7:0] SEG_DATA;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("part5_v.sdo");
// synopsys translate_on

wire \Add2~132_combout ;
wire \Add2~133 ;
wire \Add2~134_combout ;
wire \Add2~135 ;
wire \Add2~136_combout ;
wire \Add2~137 ;
wire \Add2~138_combout ;
wire \Add2~139 ;
wire \Add2~140_combout ;
wire \Add2~141 ;
wire \Add2~142_combout ;
wire \Add2~143 ;
wire \Add2~144_combout ;
wire \Add2~145 ;
wire \Add2~146_combout ;
wire \Add2~147 ;
wire \Add2~148_combout ;
wire \Add2~149 ;
wire \Add2~150_combout ;
wire \Add2~151 ;
wire \Add2~152_combout ;
wire \Add1~132_combout ;
wire \Add1~133 ;
wire \Add1~134_combout ;
wire \Add1~135 ;
wire \Add1~136_combout ;
wire \Add1~137 ;
wire \Add1~138_combout ;
wire \Add1~139 ;
wire \Add1~140_combout ;
wire \Add1~141 ;
wire \Add1~142_combout ;
wire \Add1~143 ;
wire \Add1~144_combout ;
wire \Add1~145 ;
wire \Add1~146_combout ;
wire \Add1~147 ;
wire \Add1~148_combout ;
wire \Add1~149 ;
wire \Add1~150_combout ;
wire \Add1~151 ;
wire \Add1~152_combout ;
wire \Cnt|WideOr2~64_combout ;
wire \Cnt|WideOr4~96_combout ;
wire \Cnt|WideOr3~98_combout ;
wire \SEG_DATA~3885_combout ;
wire \D4|out[0]~500_combout ;
wire \Cnt|WideOr0~49_combout ;
wire \SEG_DATA~3894_combout ;
wire \SEG_DATA~3895_combout ;
wire \SEG_DATA~3902_combout ;
wire \D2|out[2]~425_combout ;
wire \SEG_DATA~3927_combout ;
wire \D4|out[6]~503_combout ;
wire \Clock~regout ;
wire \Equal1~140_combout ;
wire \Equal1~141_combout ;
wire \Equal1~142_combout ;
wire \Equal0~140_combout ;
wire \Equal0~141_combout ;
wire \Equal0~142_combout ;
wire \Equal0~143_combout ;
wire \Clock~18_combout ;
wire \temp2~574_combout ;
wire \temp2~575_combout ;
wire \temp2~576_combout ;
wire \temp2~577_combout ;
wire \temp2~578_combout ;
wire \temp1~285_combout ;
wire \temp1~286_combout ;
wire \temp1~287_combout ;
wire \temp1~288_combout ;
wire \temp1~289_combout ;
wire \temp1~290_combout ;
wire \D1|out[1]~965_combout ;
wire \D1|out[1]~972_combout ;
wire \Clock~clkctrl_outclk ;
wire \Wren~combout ;
wire \cnt[0]~40_combout ;
wire \cnt[1]~39_combout ;
wire \cnt[2]~38_combout ;
wire \Equal2~135_combout ;
wire \SEG_DATA~3882_combout ;
wire \SEG_COM~74_combout ;
wire \Equal2~136_combout ;
wire \Equal2~137_combout ;
wire \Equal2~138_combout ;
wire \Equal2~139_combout ;
wire \Equal2~140_combout ;
wire \CLK~combout ;
wire \CLK~clkctrl_outclk ;
wire \SW_A~combout ;
wire \Cnt|y.11001~regout ;
wire \Cnt|y.11010~regout ;
wire \Cnt|y.11011~feeder_combout ;
wire \Cnt|y.11011~regout ;
wire \Cnt|y.11100~feeder_combout ;
wire \Cnt|y.11100~regout ;
wire \Cnt|y.11101~feeder_combout ;
wire \Cnt|y.11101~regout ;
wire \Cnt|y.11110~feeder_combout ;
wire \Cnt|y.11110~regout ;
wire \Cnt|y.11111~feeder_combout ;
wire \Cnt|y.11111~regout ;
wire \Cnt|y.00000~41_combout ;
wire \Cnt|y.00000~regout ;
wire \Cnt|y.00001~34_combout ;
wire \Cnt|y.00001~regout ;
wire \Cnt|y.00010~regout ;
wire \Cnt|y.00011~feeder_combout ;
wire \Cnt|y.00011~regout ;
wire \Cnt|y.00100~feeder_combout ;
wire \Cnt|y.00100~regout ;
wire \Cnt|y.00101~regout ;
wire \Cnt|y.00110~regout ;
wire \Cnt|y.00111~feeder_combout ;
wire \Cnt|y.00111~regout ;
wire \Cnt|y.01000~regout ;
wire \Cnt|y.01001~regout ;
wire \Cnt|y.01010~regout ;
wire \Cnt|y.01011~feeder_combout ;
wire \Cnt|y.01011~regout ;
wire \Cnt|y.01100~regout ;
wire \Cnt|y.01101~regout ;
wire \Cnt|y.01110~feeder_combout ;
wire \Cnt|y.01110~regout ;
wire \Cnt|y.01111~feeder_combout ;
wire \Cnt|y.01111~regout ;
wire \Cnt|y.10000~regout ;
wire \Cnt|y.10001~regout ;
wire \Cnt|y.10010~regout ;
wire \Cnt|y.10011~regout ;
wire \Cnt|y.10100~regout ;
wire \Cnt|y.10101~regout ;
wire \Cnt|y.10110~feeder_combout ;
wire \Cnt|y.10110~regout ;
wire \Cnt|y.10111~regout ;
wire \Cnt|y.11000~regout ;
wire \Cnt|WideOr4~95_combout ;
wire \Cnt|WideOr1~85_combout ;
wire \Cnt|WideOr4~97_combout ;
wire \Cnt|WideOr4~98_combout ;
wire \Cnt|WideOr3~99_combout ;
wire \Cnt|WideOr3~100_combout ;
wire \Cnt|WideOr3~101_combout ;
wire \Cnt|WideOr3~102_combout ;
wire \Cnt|WideOr2~65_combout ;
wire \Cnt|WideOr2~66_combout ;
wire \Cnt|WideOr1~86_combout ;
wire \Cnt|WideOr1~87_combout ;
wire \Cnt|WideOr0~48_combout ;
wire \Cnt|WideOr0~50_combout ;
wire \D2|out[0]~424_combout ;
wire \D3|out[0]~421_combout ;
wire \SEG_DATA~3889_combout ;
wire \D1|out[0]~966_combout ;
wire \SEG_DATA~3890_combout ;
wire \SEG_DATA~3891_combout ;
wire \SEG_DATA~3886_combout ;
wire \SEG_DATA~3887_combout ;
wire \SEG_DATA~3883_combout ;
wire \SEG_DATA~3884_combout ;
wire \SEG_DATA~3888_combout ;
wire \SEG_DATA~3892_combout ;
wire \SEG_DATA~3897_combout ;
wire \SEG_DATA~3896_combout ;
wire \SEG_DATA~3898_combout ;
wire \SEG_DATA~3942_combout ;
wire \SEG_DATA~3893_combout ;
wire \SEG_DATA~3943_combout ;
wire \SEG_DATA~3899_combout ;
wire \SEG_DATA~3900_combout ;
wire \SEG_DATA~3901_combout ;
wire \SEG_DATA~3903_combout ;
wire \SEG_DATA~3904_combout ;
wire \SEG_DATA~3905_combout ;
wire \SEG_DATA~3907_combout ;
wire \D1|out[2]~967_combout ;
wire \D3|out[2]~422_combout ;
wire \SEG_DATA~3908_combout ;
wire \SEG_DATA~3909_combout ;
wire \D5|out[2]~768_combout ;
wire \D4|out[2]~501_combout ;
wire \SEG_DATA~3906_combout ;
wire \SEG_DATA~3910_combout ;
wire \D1|out[3]~968_combout ;
wire \SEG_DATA~3941_combout ;
wire \D4|out[3]~502_combout ;
wire \D5|out[3]~769_combout ;
wire \D2|out[3]~426_combout ;
wire \D3|out[3]~423_combout ;
wire \SEG_DATA~3911_combout ;
wire \SEG_DATA~3912_combout ;
wire \SEG_DATA~3913_combout ;
wire \SEG_DATA~3918_combout ;
wire \SEG_DATA~3917_combout ;
wire \SEG_DATA~3919_combout ;
wire \D1|out[4]~969_combout ;
wire \SEG_DATA~3920_combout ;
wire \SEG_DATA~3915_combout ;
wire \SEG_DATA~3914_combout ;
wire \SEG_DATA~3916_combout ;
wire \SEG_DATA~3921_combout ;
wire \SEG_DATA~3923_combout ;
wire \SEG_DATA~3924_combout ;
wire \D1|out[5]~970_combout ;
wire \SEG_DATA~3928_combout ;
wire \SEG_DATA~3929_combout ;
wire \SEG_DATA~3930_combout ;
wire \SEG_DATA~3925_combout ;
wire \SEG_DATA~3926_combout ;
wire \SEG_DATA~3931_combout ;
wire \SEG_DATA~3932_combout ;
wire \SEG_DATA~3933_combout ;
wire \SEG_DATA~3922_combout ;
wire \SEG_DATA~3934_combout ;
wire \D5|out[6]~770_combout ;
wire \D1|out[6]~971_combout ;
wire \SEG_DATA~3938_combout ;
wire \SEG_DATA~3936_combout ;
wire \SEG_DATA~3935_combout ;
wire \SEG_DATA~3937_combout ;
wire \SEG_DATA~3939_combout ;
wire \SEG_DATA~3940_combout ;
wire [7:0] \Ram|altsyncram_component|auto_generated|q_b ;
wire [4:0] \Address~combout ;
wire [7:0] \Data~combout ;
wire [2:0] cnt;
wire [10:0] temp1;
wire [10:0] temp2;

wire [7:0] \Ram|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ;

assign \Ram|altsyncram_component|auto_generated|q_b [0] = \Ram|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0];
assign \Ram|altsyncram_component|auto_generated|q_b [1] = \Ram|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [1];
assign \Ram|altsyncram_component|auto_generated|q_b [2] = \Ram|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [2];
assign \Ram|altsyncram_component|auto_generated|q_b [3] = \Ram|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [3];
assign \Ram|altsyncram_component|auto_generated|q_b [4] = \Ram|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [4];
assign \Ram|altsyncram_component|auto_generated|q_b [5] = \Ram|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [5];
assign \Ram|altsyncram_component|auto_generated|q_b [6] = \Ram|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [6];
assign \Ram|altsyncram_component|auto_generated|q_b [7] = \Ram|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [7];

// atom is at M4K_X52_Y30
cycloneii_ram_block \Ram|altsyncram_component|auto_generated|ram_block1a0 (
	.portawe(\Wren~combout ),
	.portaaddrstall(gnd),
	.portbrewe(vcc),
	.portbaddrstall(gnd),
	.clk0(\CLK~clkctrl_outclk ),
	.clk1(gnd),
	.ena0(vcc),
	.ena1(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\Data~combout [7],\Data~combout [6],\Data~combout [5],\Data~combout [4],\Data~combout [3],\Data~combout [2],\Data~combout [1],\Data~combout [0]}),
	.portaaddr({\Address~combout [4],\Address~combout [3],\Address~combout [2],\Address~combout [1],\Address~combout [0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(8'b00000000),
	.portbaddr({\Cnt|WideOr0~50_combout ,\Cnt|WideOr1~87_combout ,\Cnt|WideOr2~66_combout ,\Cnt|WideOr3~102_combout ,\Cnt|WideOr4~98_combout }),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\Ram|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .init_file = "myram.mif";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ALTSYNCRAM";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "dual_port";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 5;
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_in_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 8;
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0;
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 31;
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32;
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock0";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 5;
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_b_byte_enable_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "none";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 8;
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0;
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 31;
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 32;
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8;
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clock = "clock0";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M4K";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .safe_write = "err_on_2clk";
defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 256'h0000000000000000000000000000000000000000000000000000010101010001;
// synopsys translate_on

// atom is at LCCOMB_X36_Y16_N2
cycloneii_lcell_comb \Add2~132 (
// Equation(s):
// \Add2~132_combout  = temp2[0] $ VCC
// \Add2~133  = CARRY(temp2[0])

	.dataa(vcc),
	.datab(temp2[0]),
	.datac(vcc),
	.datad(vcc),
	.cin(gnd),
	.combout(\Add2~132_combout ),
	.cout(\Add2~133 ));
// synopsys translate_off
defparam \Add2~132 .lut_mask = 16'h33CC;
defparam \Add2~132 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X36_Y16_N4
cycloneii_lcell_comb \Add2~134 (
// Equation(s):
// \Add2~134_combout  = temp2[1] & !\Add2~133  # !temp2[1] & (\Add2~133  # GND)
// \Add2~135  = CARRY(!\Add2~133  # !temp2[1])

	.dataa(vcc),
	.datab(temp2[1]),
	.datac(vcc),
	.datad(vcc),
	.cin(\Add2~133 ),
	.combout(\Add2~134_combout ),
	.cout(\Add2~135 ));
// synopsys translate_off
defparam \Add2~134 .lut_mask = 16'h3C3F;
defparam \Add2~134 .sum_lutc_input = "cin";
// synopsys translate_on

// atom is at LCCOMB_X36_Y16_N6
cycloneii_lcell_comb \Add2~136 (
// Equation(s):
// \Add2~136_combout  = temp2[2] & (\Add2~135  $ GND) # !temp2[2] & !\Add2~135  & VCC
// \Add2~137  = CARRY(temp2[2] & !\Add2~135 )

	.dataa(vcc),
	.datab(temp2[2]),
	.datac(vcc),
	.datad(vcc),
	.cin(\Add2~135 ),
	.combout(\Add2~136_combout ),
	.cout(\Add2~137 ));
// synopsys translate_off
defparam \Add2~136 .lut_mask = 16'hC30C;
defparam \Add2~136 .sum_lutc_input = "cin";
// synopsys translate_on

// atom is at LCCOMB_X36_Y16_N8
cycloneii_lcell_comb \Add2~138 (
// Equation(s):
// \Add2~138_combout  = temp2[3] & !\Add2~137  # !temp2[3] & (\Add2~137  # GND)
// \Add2~139  = CARRY(!\Add2~137  # !temp2[3])

	.dataa(temp2[3]),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.cin(\Add2~137 ),
	.combout(\Add2~138_combout ),
	.cout(\Add2~139 ));
// synopsys translate_off
defparam \Add2~138 .lut_mask = 16'h5A5F;
defparam \Add2~138 .sum_lutc_input = "cin";
// synopsys translate_on

// atom is at LCCOMB_X36_Y16_N10
cycloneii_lcell_comb \Add2~140 (
// Equation(s):
// \Add2~140_combout  = temp2[4] & (\Add2~139  $ GND) # !temp2[4] & !\Add2~139  & VCC
// \Add2~141  = CARRY(temp2[4] & !\Add2~139 )

	.dataa(vcc),
	.datab(temp2[4]),
	.datac(vcc),
	.datad(vcc),