part5.tan.summary

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.576 ns
From           : Wren
To             : myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~porta_we_reg
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 24.482 ns
From           : count:Cnt|y.10000
To             : SEG_DATA[3]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 19.473 ns
From           : Data[3]
To             : SEG_DATA[3]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -4.429 ns
From           : Address[3]
To             : myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~porta_address_reg3
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 131.29 MHz ( period = 7.617 ns )
From           : count:Cnt|y.10000
To             : myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~portb_address_reg2
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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