part5.tan.rpt

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

; Worst-case tco               ; N/A   ; None          ; 24.482 ns                        ; count:Cnt|y.10000 ; SEG_DATA[3]                                                                                              ; CLK        ; --       ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 19.473 ns                        ; Data[3]           ; SEG_DATA[3]                                                                                              ; --         ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -4.429 ns                        ; Address[3]        ; myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~porta_address_reg3 ; --         ; CLK      ; 0            ;
; Clock Setup: 'CLK'           ; N/A   ; None          ; 131.29 MHz ( period = 7.617 ns ) ; count:Cnt|y.10000 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_3os1:auto_generated|ram_block1a0~portb_address_reg2 ; CLK        ; CLK      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                   ;                                                                                                          ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+-------------------+----------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+