part1.tan.qmsg

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK memory memory myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_we_reg myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[0\] 200.0 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 200.0 MHz between source memory \"myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_we_reg\" and destination memory \"myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.894 ns + Longest memory memory " "Info: + Longest memory to memory delay is 2.894 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_we_reg 1 MEM M4K_X26_Y1 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X26_Y1; Fanout = 8; MEM Node = 'myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_we_reg'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/db/altsyncram_03a1.tdf" 36 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.894 ns) 2.894 ns myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[0\] 2 MEM M4K_X26_Y1 1 " "Info: 2: + IC(0.000 ns) + CELL(2.894 ns) = 2.894 ns; Loc. = M4K_X26_Y1; Fanout = 1; MEM Node = 'myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/db/altsyncram_03a1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.894 ns ( 100.00 % ) " "Info: Total cell delay = 2.894 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.894 ns" { myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg {} myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] {} } { 0.000ns 0.000ns } { 0.000ns 2.894ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.026 ns - Smallest " "Info: - Smallest clock skew is -0.026 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.735 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLK\" to destination memory is 2.735 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part1.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/part1.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns CLK~clkctrl 2 COMB CLKCTRL_G2 30 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "part1.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/part1.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.988 ns) + CELL(0.635 ns) 2.735 ns myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[0\] 3 MEM M4K_X26_Y1 1 " "Info: 3: + IC(0.988 ns) + CELL(0.635 ns) = 2.735 ns; Loc. = M4K_X26_Y1; Fanout = 1; MEM Node = 'myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.623 ns" { CLK~clkctrl myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/db/altsyncram_03a1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.634 ns ( 59.74 % ) " "Info: Total cell delay = 1.634 ns ( 59.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.101 ns ( 40.26 % ) " "Info: Total interconnect delay = 1.101 ns ( 40.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.735 ns" { CLK CLK~clkctrl myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.735 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] {} } { 0.000ns 0.000ns 0.113ns 0.988ns } { 0.000ns 0.999ns 0.000ns 0.635ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.761 ns - Longest memory " "Info: - Longest clock path from clock \"CLK\" to source memory is 2.761 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part1.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/part1.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns CLK~clkctrl 2 COMB CLKCTRL_G2 30 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "part1.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/part1.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.988 ns) + CELL(0.661 ns) 2.761 ns myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_we_reg 3 MEM M4K_X26_Y1 8 " "Info: 3: + IC(0.988 ns) + CELL(0.661 ns) = 2.761 ns; Loc. = M4K_X26_Y1; Fanout = 8; MEM Node = 'myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_we_reg'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.649 ns" { CLK~clkctrl myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/db/altsyncram_03a1.tdf" 36 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 60.12 % ) " "Info: Total cell delay = 1.660 ns ( 60.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.101 ns ( 39.88 % ) " "Info: Total interconnect delay = 1.101 ns ( 39.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.761 ns" { CLK CLK~clkctrl myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.761 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.000ns 0.113ns 0.988ns } { 0.000ns 0.999ns 0.000ns 0.661ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.735 ns" { CLK CLK~clkctrl myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.735 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] {} } { 0.000ns 0.000ns 0.113ns 0.988ns } { 0.000ns 0.999ns 0.000ns 0.635ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.761 ns" { CLK CLK~clkctrl myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.761 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.000ns 0.113ns 0.988ns } { 0.000ns 0.999ns 0.000ns 0.661ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.209 ns + " "Info: + Micro clock to output delay of source is 0.209 ns" {  } { { "db/altsyncram_03a1.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/db/altsyncram_03a1.tdf" 36 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.035 ns + " "Info: + Micro setup delay of destination is 0.035 ns" {  } { { "db/altsyncram_03a1.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/db/altsyncram_03a1.tdf" 32 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.894 ns" { myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg {} myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] {} } { 0.000ns 0.000ns } { 0.000ns 2.894ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.735 ns" { CLK CLK~clkctrl myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.735 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] {} } { 0.000ns 0.000ns 0.113ns 0.988ns } { 0.000ns 0.999ns 0.000ns 0.635ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.761 ns" { CLK CLK~clkctrl myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.761 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.000ns 0.113ns 0.988ns } { 0.000ns 0.999ns 0.000ns 0.661ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] {} } { 0.000ns } { 0.088ns } "" } } { "db/altsyncram_03a1.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/db/altsyncram_03a1.tdf" 32 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_datain_reg0 Data\[0\] CLK 3.829 ns memory " "Info: tsu for memory \"myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_datain_reg0\" (data pin = \"Data\[0\]\", clock pin = \"CLK\") is 3.829 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.554 ns + Longest pin memory " "Info: + Longest pin to memory delay is 6.554 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.830 ns) 0.830 ns Data\[0\] 1 PIN PIN_Y13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_Y13; Fanout = 1; PIN Node = 'Data\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { Data[0] } "NODE_NAME" } } { "part1.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/part1.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.618 ns) + CELL(0.106 ns) 6.554 ns myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_datain_reg0 2 MEM M4K_X26_Y1 1 " "Info: 2: + IC(5.618 ns) + CELL(0.106 ns) = 6.554 ns; Loc. = M4K_X26_Y1; Fanout = 1; MEM Node = 'myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_datain_reg0'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.724 ns" { Data[0] myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/db/altsyncram_03a1.tdf" 36 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.936 ns ( 14.28 % ) " "Info: Total cell delay = 0.936 ns ( 14.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.618 ns ( 85.72 % ) " "Info: Total interconnect delay = 5.618 ns ( 85.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.554 ns" { Data[0] myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "6.554 ns" { Data[0] {} Data[0]~combout {} myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0 {} } { 0.000ns 0.000ns 5.618ns } { 0.000ns 0.830ns 0.106ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.035 ns + " "Info: + Micro setup delay of destination is 0.035 ns" {  } { { "db/altsyncram_03a1.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/db/altsyncram_03a1.tdf" 36 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.760 ns - Shortest memory " "Info: - Shortest clock path from clock \"CLK\" to destination memory is 2.760 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part1.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/part1.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns CLK~clkctrl 2 COMB CLKCTRL_G2 30 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "part1.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/part1.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.988 ns) + CELL(0.660 ns) 2.760 ns myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_datain_reg0 3 MEM M4K_X26_Y1 1 " "Info: 3: + IC(0.988 ns) + CELL(0.660 ns) = 2.760 ns; Loc. = M4K_X26_Y1; Fanout = 1; MEM Node = 'myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_datain_reg0'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.648 ns" { CLK~clkctrl myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/db/altsyncram_03a1.tdf" 36 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.659 ns ( 60.11 % ) " "Info: Total cell delay = 1.659 ns ( 60.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.101 ns ( 39.89 % ) " "Info: Total interconnect delay = 1.101 ns ( 39.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.760 ns" { CLK CLK~clkctrl myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.760 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0 {} } { 0.000ns 0.000ns 0.113ns 0.988ns } { 0.000ns 0.999ns 0.000ns 0.660ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.554 ns" { Data[0] myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "6.554 ns" { Data[0] {} Data[0]~combout {} myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0 {} } { 0.000ns 0.000ns 5.618ns } { 0.000ns 0.830ns 0.106ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.760 ns" { CLK CLK~clkctrl myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.760 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0 {} } { 0.000ns 0.000ns 0.113ns 0.988ns } { 0.000ns 0.999ns 0.000ns 0.660ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK LED\[6\] myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[6\] 7.624 ns memory " "Info: tco from clock \"CLK\" to destination pin \"LED\[6\]\" through memory \"myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[6\]\" is 7.624 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.735 ns + Longest memory " "Info: + Longest clock path from clock \"CLK\" to source memory is 2.735 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part1.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/part1.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns CLK~clkctrl 2 COMB CLKCTRL_G2 30 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "part1.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/part1.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.988 ns) + CELL(0.635 ns) 2.735 ns myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[6\] 3 MEM M4K_X26_Y1 1 " "Info: 3: + IC(0.988 ns) + CELL(0.635 ns) = 2.735 ns; Loc. = M4K_X26_Y1; Fanout = 1; MEM Node = 'myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[6\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.623 ns" { CLK~clkctrl myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/db/altsyncram_03a1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.634 ns ( 59.74 % ) " "Info: Total cell delay = 1.634 ns ( 59.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.101 ns ( 40.26 % ) " "Info: Total interconnect delay = 1.101 ns ( 40.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.735 ns" { CLK CLK~clkctrl myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.735 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] {} } { 0.000ns 0.000ns 0.113ns 0.988ns } { 0.000ns 0.999ns 0.000ns 0.635ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.209 ns + " "Info: + Micro clock to output delay of source is 0.209 ns" {  } { { "db/altsyncram_03a1.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/db/altsyncram_03a1.tdf" 32 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.680 ns + Longest memory pin " "Info: + Longest memory to pin delay is 4.680 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.088 ns) 0.088 ns myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[6\] 1 MEM M4K_X26_Y1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.088 ns) = 0.088 ns; Loc. = M4K_X26_Y1; Fanout = 1; MEM Node = 'myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[6\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/db/altsyncram_03a1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.794 ns) + CELL(2.798 ns) 4.680 ns LED\[6\] 2 PIN PIN_AD7 0 " "Info: 2: + IC(1.794 ns) + CELL(2.798 ns) = 4.680 ns; Loc. = PIN_AD7; Fanout = 0; PIN Node = 'LED\[6\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.592 ns" { myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] LED[6] } "NODE_NAME" } } { "part1.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/part1.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.886 ns ( 61.67 % ) " "Info: Total cell delay = 2.886 ns ( 61.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.794 ns ( 38.33 % ) " "Info: Total interconnect delay = 1.794 ns ( 38.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.680 ns" { myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] LED[6] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.680 ns" { myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] {} LED[6] {} } { 0.000ns 1.794ns } { 0.088ns 2.798ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.735 ns" { CLK CLK~clkctrl myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.735 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] {} } { 0.000ns 0.000ns 0.113ns 0.988ns } { 0.000ns 0.999ns 0.000ns 0.635ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.680 ns" { myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] LED[6] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.680 ns" { myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] {} LED[6] {} } { 0.000ns 1.794ns } { 0.088ns 2.798ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_datain_reg1 Data\[1\] CLK -2.826 ns memory " "Info: th for memory \"myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_datain_reg1\" (data pin = \"Data\[1\]\", clock pin = \"CLK\") is -2.826 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.760 ns + Longest memory " "Info: + Longest clock path from clock \"CLK\" to destination memory is 2.760 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part1.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/part1.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns CLK~clkctrl 2 COMB CLKCTRL_G2 30 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "part1.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/part1.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.988 ns) + CELL(0.660 ns) 2.760 ns myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_datain_reg1 3 MEM M4K_X26_Y1 1 " "Info: 3: + IC(0.988 ns) + CELL(0.660 ns) = 2.760 ns; Loc. = M4K_X26_Y1; Fanout = 1; MEM Node = 'myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_datain_reg1'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.648 ns" { CLK~clkctrl myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1 } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/db/altsyncram_03a1.tdf" 36 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.659 ns ( 60.11 % ) " "Info: Total cell delay = 1.659 ns ( 60.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.101 ns ( 39.89 % ) " "Info: Total interconnect delay = 1.101 ns ( 39.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.760 ns" { CLK CLK~clkctrl myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.760 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1 {} } { 0.000ns 0.000ns 0.113ns 0.988ns } { 0.000ns 0.999ns 0.000ns 0.660ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.234 ns + " "Info: + Micro hold delay of destination is 0.234 ns" {  } { { "db/altsyncram_03a1.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/db/altsyncram_03a1.tdf" 36 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.820 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 5.820 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.820 ns) 0.820 ns Data\[1\] 1 PIN PIN_AB12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.820 ns) = 0.820 ns; Loc. = PIN_AB12; Fanout = 1; PIN Node = 'Data\[1\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { Data[1] } "NODE_NAME" } } { "part1.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/part1.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.894 ns) + CELL(0.106 ns) 5.820 ns myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_datain_reg1 2 MEM M4K_X26_Y1 1 " "Info: 2: + IC(4.894 ns) + CELL(0.106 ns) = 5.820 ns; Loc. = M4K_X26_Y1; Fanout = 1; MEM Node = 'myram1:Ram\|altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_datain_reg1'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { Data[1] myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1 } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part1/db/altsyncram_03a1.tdf" 36 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.926 ns ( 15.91 % ) " "Info: Total cell delay = 0.926 ns ( 15.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.894 ns ( 84.09 % ) " "Info: Total interconnect delay = 4.894 ns ( 84.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.820 ns" { Data[1] myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "5.820 ns" { Data[1] {} Data[1]~combout {} myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1 {} } { 0.000ns 0.000ns 4.894ns } { 0.000ns 0.820ns 0.106ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.760 ns" { CLK CLK~clkctrl myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.760 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1 {} } { 0.000ns 0.000ns 0.113ns 0.988ns } { 0.000ns 0.999ns 0.000ns 0.660ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.820 ns" { Data[1] myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "5.820 ns" { Data[1] {} Data[1]~combout {} myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1 {} } { 0.000ns 0.000ns 4.894ns } { 0.000ns 0.820ns 0.106ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}