part1.tan.summary

来自「This codes is one of my univ projects I 」· SUMMARY 代码 · 共 57 行

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.829 ns
From           : Data[0]
To             : myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 7.624 ns
From           : myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]
To             : LED[6]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.826 ns
From           : Data[1]
To             : myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 200.00 MHz ( period = 5.000 ns )
From           : myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4
To             : myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[7]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------