part1.vo

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

// Copyright (C) 1991-2008 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 8.1 Build 163 10/28/2008 SJ Web Edition"

// DATE "05/22/2009 09:24:30"

// 
// Device: Altera EP2C35F672C6 Package FBGA672
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module part1 (
	CLK,
	Address,
	Data,
	Wren,
	LED);
input 	CLK;
input 	[4:0] Address;
input 	[7:0] Data;
input 	Wren;
output 	[7:0] LED;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("part1_v.sdo");
// synopsys translate_on

wire \Wren~combout ;
wire \CLK~combout ;
wire \CLK~clkctrl_outclk ;
wire [7:0] \Ram|altsyncram_component|auto_generated|q_a ;
wire [4:0] \Address~combout ;
wire [7:0] \Data~combout ;

wire [7:0] \Ram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;

assign \Ram|altsyncram_component|auto_generated|q_a [0] = \Ram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];
assign \Ram|altsyncram_component|auto_generated|q_a [1] = \Ram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1];
assign \Ram|altsyncram_component|auto_generated|q_a [2] = \Ram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2];
assign \Ram|altsyncram_component|auto_generated|q_a [3] = \Ram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3];
assign \Ram|altsyncram_component|auto_generated|q_a [4] = \Ram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4];
assign \Ram|altsyncram_component|auto_generated|q_a [5] = \Ram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5];
assign \Ram|altsyncram_component|auto_generated|q_a [6] = \Ram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6];
assign \Ram|altsyncram_component|auto_generated|q_a [7] = \Ram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7];

// atom is at PIN_W11
cycloneii_io \Wren~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\Wren~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(Wren));
// synopsys translate_off
defparam \Wren~I .input_async_reset = "none";
defparam \Wren~I .input_power_up = "low";
defparam \Wren~I .input_register_mode = "none";
defparam \Wren~I .input_sync_reset = "none";
defparam \Wren~I .oe_async_reset = "none";
defparam \Wren~I .oe_power_up = "low";
defparam \Wren~I .oe_register_mode = "none";
defparam \Wren~I .oe_sync_reset = "none";
defparam \Wren~I .operation_mode = "input";
defparam \Wren~I .output_async_reset = "none";
defparam \Wren~I .output_power_up = "low";
defparam \Wren~I .output_register_mode = "none";
defparam \Wren~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_N1
cycloneii_io \CLK~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\CLK~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(CLK));
// synopsys translate_off
defparam \CLK~I .input_async_reset = "none";
defparam \CLK~I .input_power_up = "low";
defparam \CLK~I .input_register_mode = "none";
defparam \CLK~I .input_sync_reset = "none";
defparam \CLK~I .oe_async_reset = "none";
defparam \CLK~I .oe_power_up = "low";
defparam \CLK~I .oe_register_mode = "none";
defparam \CLK~I .oe_sync_reset = "none";
defparam \CLK~I .operation_mode = "input";
defparam \CLK~I .output_async_reset = "none";
defparam \CLK~I .output_power_up = "low";
defparam \CLK~I .output_register_mode = "none";
defparam \CLK~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at CLKCTRL_G2
cycloneii_clkctrl \CLK~clkctrl (
	.ena(vcc),
	.inclk({gnd,gnd,gnd,\CLK~combout }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\CLK~clkctrl_outclk ));
// synopsys translate_off
defparam \CLK~clkctrl .clock_type = "global clock";
defparam \CLK~clkctrl .ena_register_mode = "falling edge";
// synopsys translate_on

// atom is at PIN_Y13
cycloneii_io \Data[0]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\Data~combout [0]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(Data[0]));
// synopsys translate_off
defparam \Data[0]~I .input_async_reset = "none";
defparam \Data[0]~I .input_power_up = "low";
defparam \Data[0]~I .input_register_mode = "none";
defparam \Data[0]~I .input_sync_reset = "none";
defparam \Data[0]~I .oe_async_reset = "none";
defparam \Data[0]~I .oe_power_up = "low";
defparam \Data[0]~I .oe_register_mode = "none";
defparam \Data[0]~I .oe_sync_reset = "none";
defparam \Data[0]~I .operation_mode = "input";
defparam \Data[0]~I .output_async_reset = "none";
defparam \Data[0]~I .output_power_up = "low";
defparam \Data[0]~I .output_register_mode = "none";
defparam \Data[0]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_W12
cycloneii_io \Address[0]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\Address~combout [0]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(Address[0]));
// synopsys translate_off
defparam \Address[0]~I .input_async_reset = "none";
defparam \Address[0]~I .input_power_up = "low";
defparam \Address[0]~I .input_register_mode = "none";
defparam \Address[0]~I .input_sync_reset = "none";
defparam \Address[0]~I .oe_async_reset = "none";
defparam \Address[0]~I .oe_power_up = "low";
defparam \Address[0]~I .oe_register_mode = "none";
defparam \Address[0]~I .oe_sync_reset = "none";
defparam \Address[0]~I .operation_mode = "input";
defparam \Address[0]~I .output_async_reset = "none";
defparam \Address[0]~I .output_power_up = "low";
defparam \Address[0]~I .output_register_mode = "none";
defparam \Address[0]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_AA11
cycloneii_io \Address[1]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\Address~combout [1]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(Address[1]));
// synopsys translate_off
defparam \Address[1]~I .input_async_reset = "none";
defparam \Address[1]~I .input_power_up = "low";
defparam \Address[1]~I .input_register_mode = "none";
defparam \Address[1]~I .input_sync_reset = "none";
defparam \Address[1]~I .oe_async_reset = "none";
defparam \Address[1]~I .oe_power_up = "low";
defparam \Address[1]~I .oe_register_mode = "none";
defparam \Address[1]~I .oe_sync_reset = "none";
defparam \Address[1]~I .operation_mode = "input";
defparam \Address[1]~I .output_async_reset = "none";
defparam \Address[1]~I .output_power_up = "low";
defparam \Address[1]~I .output_register_mode = "none";
defparam \Address[1]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_Y11
cycloneii_io \Address[2]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\Address~combout [2]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(Address[2]));
// synopsys translate_off
defparam \Address[2]~I .input_async_reset = "none";
defparam \Address[2]~I .input_power_up = "low";
defparam \Address[2]~I .input_register_mode = "none";
defparam \Address[2]~I .input_sync_reset = "none";
defparam \Address[2]~I .oe_async_reset = "none";
defparam \Address[2]~I .oe_power_up = "low";
defparam \Address[2]~I .oe_register_mode = "none";
defparam \Address[2]~I .oe_sync_reset = "none";
defparam \Address[2]~I .operation_mode = "input";
defparam \Address[2]~I .output_async_reset = "none";
defparam \Address[2]~I .output_power_up = "low";
defparam \Address[2]~I .output_register_mode = "none";
defparam \Address[2]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_AD11
cycloneii_io \Address[3]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\Address~combout [3]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(Address[3]));
// synopsys translate_off