part1_v.sdo

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

// Copyright (C) 1991-2008 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP2C35F672C6 Package FBGA672
// 

// 
// This SDF file should be used for ModelSim (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "part1")
  (DATE "05/22/2009 09:24:30")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 8.1 Build 163 10/28/2008 SJ Web Edition")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE Wren\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (850:850:850) (850:850:850))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE CLK\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (999:999:999) (999:999:999))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_clkctrl")
    (INSTANCE CLK\~clkctrl)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (113:113:113) (113:113:113))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ena_reg")
    (INSTANCE CLK\~clkctrl.extena0_reg)
    (DELAY
      (ABSOLUTE
        (PORT d (254:254:254) (254:254:254))
        (PORT clk (0:0:0) (0:0:0))
        (IOPATH (posedge clk) q (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (50:50:50))
      (HOLD d (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE Data\[0\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (830:830:830) (830:830:830))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE Address\[0\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (850:850:850) (850:850:850))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE Address\[1\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (820:820:820) (820:820:820))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE Address\[2\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (810:810:810) (810:810:810))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE Address\[3\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (850:850:850) (850:850:850))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE Address\[4\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (840:840:840) (840:840:840))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE Data\[1\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (820:820:820) (820:820:820))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE Data\[2\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (820:820:820) (820:820:820))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE Data\[3\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (850:850:850) (850:850:850))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE Data\[4\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (830:830:830) (830:830:830))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE Data\[5\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (840:840:840) (840:840:840))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE Data\[6\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (850:850:850) (850:850:850))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE Data\[7\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (810:810:810) (810:810:810))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (5724:5724:5724) (5724:5724:5724))
        (PORT d[1] (5000:5000:5000) (5000:5000:5000))
        (PORT d[2] (5234:5234:5234) (5234:5234:5234))
        (PORT d[3] (5468:5468:5468) (5468:5468:5468))
        (PORT d[4] (4996:4996:4996) (4996:4996:4996))
        (PORT d[5] (5255:5255:5255) (5255:5255:5255))
        (PORT d[6] (5247:5247:5247) (5247:5247:5247))
        (PORT d[7] (5240:5240:5240) (5240:5240:5240))
        (PORT clk (1648:1648:1648) (1648:1648:1648))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (35:35:35))
      (HOLD d (posedge clk) (234:234:234))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (5494:5494:5494) (5494:5494:5494))
        (PORT d[1] (5727:5727:5727) (5727:5727:5727))
        (PORT d[2] (5726:5726:5726) (5726:5726:5726))
        (PORT d[3] (5035:5035:5035) (5035:5035:5035))
        (PORT d[4] (5277:5277:5277) (5277:5277:5277))
        (PORT clk (1649:1649:1649) (1649:1649:1649))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (35:35:35))
      (HOLD d (posedge clk) (234:234:234))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (5668:5668:5668) (5668:5668:5668))
        (PORT clk (1649:1649:1649) (1649:1649:1649))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (35:35:35))
      (HOLD d (posedge clk) (234:234:234))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|ram_block1a0.active_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1649:1649:1649) (1649:1649:1649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1858:1858:1858) (1858:1858:1858))
        (IOPATH (posedge clk) pulse (0:0:0) (1011:1011:1011))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1858:1858:1858) (1858:1858:1858))
        (IOPATH (posedge clk) pulse (0:0:0) (2024:2024:2024))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1858:1858:1858) (1858:1858:1858))
        (IOPATH (posedge clk) pulse (0:0:0) (2894:2894:2894))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1623:1623:1623) (1623:1623:1623))
        (IOPATH (posedge clk) q (297:297:297) (297:297:297))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (35:35:35))
      (HOLD d (posedge clk) (234:234:234))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE LED\[0\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (1000:1000:1000) (1000:1000:1000))
        (IOPATH datain padio (2808:2808:2808) (2808:2808:2808))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE LED\[1\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (996:996:996) (996:996:996))
        (IOPATH datain padio (2808:2808:2808) (2808:2808:2808))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE LED\[2\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (1487:1487:1487) (1487:1487:1487))
        (IOPATH datain padio (2798:2798:2798) (2798:2798:2798))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE LED\[3\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (1636:1636:1636) (1636:1636:1636))
        (IOPATH datain padio (2828:2828:2828) (2828:2828:2828))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE LED\[4\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (1467:1467:1467) (1467:1467:1467))
        (IOPATH datain padio (2808:2808:2808) (2808:2808:2808))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE LED\[5\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (1480:1480:1480) (1480:1480:1480))
        (IOPATH datain padio (2808:2808:2808) (2808:2808:2808))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE LED\[6\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (1794:1794:1794) (1794:1794:1794))
        (IOPATH datain padio (2798:2798:2798) (2798:2798:2798))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE LED\[7\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (1699:1699:1699) (1699:1699:1699))
        (IOPATH datain padio (2788:2788:2788) (2788:2788:2788))
      )
    )
  )
)