📄 part1.flow.rpt
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Flow report for part1
Fri May 22 09:24:30 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+-----------------------------------------+
; Flow Status ; Successful - Fri May 22 09:24:30 2009 ;
; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Web Edition ;
; Revision Name ; part1 ;
; Top-level Entity Name ; part1 ;
; Family ; Cyclone II ;
; Device ; EP2C35F672C6 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
; Total logic elements ; 0 / 33,216 ( 0 % ) ;
; Total combinational functions ; 0 / 33,216 ( 0 % ) ;
; Dedicated logic registers ; 0 / 33,216 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 23 / 475 ( 5 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 256 / 483,840 ( < 1 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+-----------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 05/22/2009 09:22:49 ;
; Main task ; Compilation ;
; Revision Name ; part1 ;
+-------------------+---------------------+
+---------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+---------------------------------+------------------------------+---------------+-------------+----------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------+------------------------------+---------------+-------------+----------------------+
; COMPILER_SIGNATURE_ID ; 110901736380.124295176904524 ; -- ; -- ; -- ;
; EDA_DESIGN_ENTRY_SYNTHESIS_TOOL ; Synplify Pro ; <None> ; -- ; -- ;
; EDA_INPUT_DATA_FORMAT ; Vqm ; -- ; -- ; eda_design_synthesis ;
; EDA_LMF_FILE ; synplcty.lmf ; -- ; -- ; eda_design_synthesis ;
; EDA_OUTPUT_DATA_FORMAT ; Verilog ; -- ; -- ; eda_simulation ;
; EDA_OUTPUT_DATA_FORMAT ; Verilog ; -- ; -- ; eda_timing_analysis ;
; EDA_SIMULATION_TOOL ; ModelSim (Verilog) ; <None> ; -- ; -- ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; EDA_TIMING_ANALYSIS_TOOL ; PrimeTime (Verilog) ; <None> ; -- ; -- ;
; PARTITION_COLOR ; 2147039 ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
+---------------------------------+------------------------------+---------------+-------------+----------------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:12 ; 1.0 ; 187 MB ; 00:00:02 ;
; Fitter ; 00:00:32 ; 1.0 ; 248 MB ; 00:00:17 ;
; Assembler ; 00:00:09 ; 1.0 ; 231 MB ; 00:00:07 ;
; Classic Timing Analyzer ; 00:00:01 ; 1.0 ; 135 MB ; 00:00:01 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 140 MB ; 00:00:01 ;
; Total ; 00:00:55 ; -- ; -- ; 00:00:28 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------------+
; Flow OS Summary ;
+-------------------------+------------------+---------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+-------------------------+------------------+---------------+------------+----------------+
; Analysis & Synthesis ; Sophy-PC ; Windows Vista ; 6.0 ; i686 ;
; Fitter ; Sophy-PC ; Windows Vista ; 6.0 ; i686 ;
; Assembler ; Sophy-PC ; Windows Vista ; 6.0 ; i686 ;
; Classic Timing Analyzer ; Sophy-PC ; Windows Vista ; 6.0 ; i686 ;
; EDA Netlist Writer ; Sophy-PC ; Windows Vista ; 6.0 ; i686 ;
+-------------------------+------------------+---------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off part1 -c part1
quartus_fit --read_settings_files=off --write_settings_files=off part1 -c part1
quartus_asm --read_settings_files=off --write_settings_files=off part1 -c part1
quartus_tan --read_settings_files=off --write_settings_files=off part1 -c part1 --timing_analysis_only
quartus_eda --read_settings_files=off --write_settings_files=off part1 -c part1
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