📄 part1.sim.rpt
字号:
; Total output ports with no 1/0-value coverage ; 15 ;
; Total output ports with no 1-value coverage ; 15 ;
; Total output ports with no 0-value coverage ; 15 ;
+-----------------------------------------------------+--------------+
The following table displays output ports that toggle between 1 and 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage ;
+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------+
; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0 ; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|q_a[0] ; portadataout0 ;
; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0 ; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|q_a[1] ; portadataout1 ;
; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0 ; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|q_a[2] ; portadataout2 ;
; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0 ; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|q_a[3] ; portadataout3 ;
; |part1|LED[0] ; |part1|LED[0] ; padio ;
; |part1|LED[1] ; |part1|LED[1] ; padio ;
; |part1|LED[2] ; |part1|LED[2] ; padio ;
; |part1|LED[3] ; |part1|LED[3] ; padio ;
; |part1|Wren ; |part1|Wren ; combout ;
; |part1|CLK ; |part1|CLK ; combout ;
; |part1|Data[0] ; |part1|Data[0] ; combout ;
; |part1|Address[0] ; |part1|Address[0] ; combout ;
; |part1|Address[1] ; |part1|Address[1] ; combout ;
; |part1|Data[1] ; |part1|Data[1] ; combout ;
; |part1|Data[2] ; |part1|Data[2] ; combout ;
; |part1|Data[3] ; |part1|Data[3] ; combout ;
; |part1|CLK~clkctrl ; |part1|CLK~clkctrl ; outclk ;
+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------+
; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0 ; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|q_a[4] ; portadataout4 ;
; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0 ; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|q_a[5] ; portadataout5 ;
; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0 ; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|q_a[6] ; portadataout6 ;
; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0 ; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|q_a[7] ; portadataout7 ;
; |part1|LED[4] ; |part1|LED[4] ; padio ;
; |part1|LED[5] ; |part1|LED[5] ; padio ;
; |part1|LED[6] ; |part1|LED[6] ; padio ;
; |part1|LED[7] ; |part1|LED[7] ; padio ;
; |part1|Address[2] ; |part1|Address[2] ; combout ;
; |part1|Address[3] ; |part1|Address[3] ; combout ;
; |part1|Address[4] ; |part1|Address[4] ; combout ;
; |part1|Data[4] ; |part1|Data[4] ; combout ;
; |part1|Data[5] ; |part1|Data[5] ; combout ;
; |part1|Data[6] ; |part1|Data[6] ; combout ;
; |part1|Data[7] ; |part1|Data[7] ; combout ;
+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------+
; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0 ; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|q_a[4] ; portadataout4 ;
; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0 ; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|q_a[5] ; portadataout5 ;
; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0 ; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|q_a[6] ; portadataout6 ;
; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0 ; |part1|myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|q_a[7] ; portadataout7 ;
; |part1|LED[4] ; |part1|LED[4] ; padio ;
; |part1|LED[5] ; |part1|LED[5] ; padio ;
; |part1|LED[6] ; |part1|LED[6] ; padio ;
; |part1|LED[7] ; |part1|LED[7] ; padio ;
; |part1|Address[2] ; |part1|Address[2] ; combout ;
; |part1|Address[3] ; |part1|Address[3] ; combout ;
; |part1|Address[4] ; |part1|Address[4] ; combout ;
; |part1|Data[4] ; |part1|Data[4] ; combout ;
; |part1|Data[5] ; |part1|Data[5] ; combout ;
; |part1|Data[6] ; |part1|Data[6] ; combout ;
; |part1|Data[7] ; |part1|Data[7] ; combout ;
+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Tue May 29 23:36:56 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off part1 -c part1
Info: Using vector source file "D:/傈傍/3切斥1切扁/叼瘤判角氰/Quartus/角嚼12/1/part1.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 53.13 %
Info: Number of transitions in simulation is 436
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Allocated 114 megabytes of memory during processing
Info: Processing ended: Tue May 29 23:36:56 2007
Info: Elapsed time: 00:00:00
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -