part6.tan.qmsg

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

{ "Info" "ITDB_FULL_TPD_RESULT" "Data\[7\] SEG_DATA\[6\] 16.962 ns Longest " "Info: Longest tpd from source pin \"Data\[7\]\" to destination pin \"SEG_DATA\[6\]\" is 16.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.810 ns) 0.810 ns Data\[7\] 1 PIN PIN_Y12 8 " "Info: 1: + IC(0.000 ns) + CELL(0.810 ns) = 0.810 ns; Loc. = PIN_Y12; Fanout = 8; PIN Node = 'Data\[7\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { Data[7] } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.028 ns) + CELL(0.420 ns) 7.258 ns display:D4\|out\[6\]~525 2 COMB LCCOMB_X42_Y12_N18 1 " "Info: 2: + IC(6.028 ns) + CELL(0.420 ns) = 7.258 ns; Loc. = LCCOMB_X42_Y12_N18; Fanout = 1; COMB Node = 'display:D4\|out\[6\]~525'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.448 ns" { Data[7] display:D4|out[6]~525 } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 160 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.651 ns) + CELL(0.275 ns) 8.184 ns SEG_DATA~3491 3 COMB LCCOMB_X44_Y12_N26 1 " "Info: 3: + IC(0.651 ns) + CELL(0.275 ns) = 8.184 ns; Loc. = LCCOMB_X44_Y12_N26; Fanout = 1; COMB Node = 'SEG_DATA~3491'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.926 ns" { display:D4|out[6]~525 SEG_DATA~3491 } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.438 ns) 9.071 ns SEG_DATA~3492 4 COMB LCCOMB_X44_Y12_N28 1 " "Info: 4: + IC(0.449 ns) + CELL(0.438 ns) = 9.071 ns; Loc. = LCCOMB_X44_Y12_N28; Fanout = 1; COMB Node = 'SEG_DATA~3492'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.887 ns" { SEG_DATA~3491 SEG_DATA~3492 } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.688 ns) + CELL(0.149 ns) 9.908 ns SEG_DATA~3493 5 COMB LCCOMB_X42_Y12_N20 1 " "Info: 5: + IC(0.688 ns) + CELL(0.149 ns) = 9.908 ns; Loc. = LCCOMB_X42_Y12_N20; Fanout = 1; COMB Node = 'SEG_DATA~3493'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { SEG_DATA~3492 SEG_DATA~3493 } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.275 ns) + CELL(2.779 ns) 16.962 ns SEG_DATA\[6\] 6 PIN PIN_AA6 0 " "Info: 6: + IC(4.275 ns) + CELL(2.779 ns) = 16.962 ns; Loc. = PIN_AA6; Fanout = 0; PIN Node = 'SEG_DATA\[6\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.054 ns" { SEG_DATA~3493 SEG_DATA[6] } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.871 ns ( 28.72 % ) " "Info: Total cell delay = 4.871 ns ( 28.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.091 ns ( 71.28 % ) " "Info: Total interconnect delay = 12.091 ns ( 71.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "16.962 ns" { Data[7] display:D4|out[6]~525 SEG_DATA~3491 SEG_DATA~3492 SEG_DATA~3493 SEG_DATA[6] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "16.962 ns" { Data[7] {} Data[7]~combout {} display:D4|out[6]~525 {} SEG_DATA~3491 {} SEG_DATA~3492 {} SEG_DATA~3493 {} SEG_DATA[6] {} } { 0.000ns 0.000ns 6.028ns 0.651ns 0.449ns 0.688ns 4.275ns } { 0.000ns 0.810ns 0.420ns 0.275ns 0.438ns 0.149ns 2.779ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "sld_hub:sld_hub_inst\|tdo_bypass_reg altera_internal_jtag~TDIUTAP altera_internal_jtag~TCKUTAP 1.962 ns register " "Info: th for register \"sld_hub:sld_hub_inst\|tdo_bypass_reg\" (data pin = \"altera_internal_jtag~TDIUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 1.962 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.430 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 4.430 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.874 ns) + CELL(0.000 ns) 2.874 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 118 " "Info: 2: + IC(2.874 ns) + CELL(0.000 ns) = 2.874 ns; Loc. = CLKCTRL_G3; Fanout = 118; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.874 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.019 ns) + CELL(0.537 ns) 4.430 ns sld_hub:sld_hub_inst\|tdo_bypass_reg 3 REG LCFF_X37_Y20_N13 2 " "Info: 3: + IC(1.019 ns) + CELL(0.537 ns) = 4.430 ns; Loc. = LCFF_X37_Y20_N13; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|tdo_bypass_reg'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.556 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|tdo_bypass_reg } "NODE_NAME" } } { "../../../../../altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 310 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 12.12 % ) " "Info: Total cell delay = 0.537 ns ( 12.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.893 ns ( 87.88 % ) " "Info: Total interconnect delay = 3.893 ns ( 87.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.430 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|tdo_bypass_reg } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.430 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|tdo_bypass_reg {} } { 0.000ns 2.874ns 1.019ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "../../../../../altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 310 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.734 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.734 ns" { { "Info" "ITDB_NODE_DE