part6.tan.qmsg

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[4\] register sld_hub:sld_hub_inst\|tdo 189.61 MHz 5.274 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 189.61 MHz between source register \"sld_hub:sld_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[4\]\" and destination register \"sld_hub:sld_hub_inst\|tdo\" (period= 5.274 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.425 ns + Longest register register " "Info: + Longest register to register delay is 2.425 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[4\] 1 REG LCFF_X40_Y20_N25 27 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X40_Y20_N25; Fanout = 27; REG Node = 'sld_hub:sld_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[4\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] } "NODE_NAME" } } { "../../../../../altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 1002 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.757 ns) + CELL(0.416 ns) 1.173 ns sld_hub:sld_hub_inst\|tdo~423 2 COMB LCCOMB_X44_Y20_N4 1 " "Info: 2: + IC(0.757 ns) + CELL(0.416 ns) = 1.173 ns; Loc. = LCCOMB_X44_Y20_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|tdo~423'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.173 ns" { sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] sld_hub:sld_hub_inst|tdo~423 } "NODE_NAME" } } { "../../../../../altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 321 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.251 ns) + CELL(0.275 ns) 1.699 ns sld_hub:sld_hub_inst\|tdo~424 3 COMB LCCOMB_X44_Y20_N0 1 " "Info: 3: + IC(0.251 ns) + CELL(0.275 ns) = 1.699 ns; Loc. = LCCOMB_X44_Y20_N0; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|tdo~424'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.526 ns" { sld_hub:sld_hub_inst|tdo~423 sld_hub:sld_hub_inst|tdo~424 } "NODE_NAME" } } { "../../../../../altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 321 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.264 ns) + CELL(0.378 ns) 2.341 ns sld_hub:sld_hub_inst\|tdo~426 4 COMB LCCOMB_X44_Y20_N10 1 " "Info: 4: + IC(0.264 ns) + CELL(0.378 ns) = 2.341 ns; Loc. = LCCOMB_X44_Y20_N10; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|tdo~426'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.642 ns" { sld_hub:sld_hub_inst|tdo~424 sld_hub:sld_hub_inst|tdo~426 } "NODE_NAME" } } { "../../../../../altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 321 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.425 ns sld_hub:sld_hub_inst\|tdo 5 REG LCFF_X44_Y20_N11 2 " "Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 2.425 ns; Loc. = LCFF_X44_Y20_N11; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|tdo'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { sld_hub:sld_hub_inst|tdo~426 sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "../../../../../altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 321 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.153 ns ( 47.55 % ) " "Info: Total cell delay = 1.153 ns ( 47.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.272 ns ( 52.45 % ) " "Info: Total interconnect delay = 1.272 ns ( 52.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.425 ns" { sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] sld_hub:sld_hub_inst|tdo~423 sld_hub:sld_hub_inst|tdo~424 sld_hub:sld_hub_inst|tdo~426 sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.425 ns" { sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] {} sld_hub:sld_hub_inst|tdo~423 {} sld_hub:sld_hub_inst|tdo~424 {} sld_hub:sld_hub_inst|tdo~426 {} sld_hub:sld_hub_inst|tdo {} } { 0.000ns 0.757ns 0.251ns 0.264ns 0.000ns } { 0.000ns 0.416ns 0.275ns 0.378ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.002 ns - Smallest " "Info: - Smallest clock skew is 0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.437 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 4.437 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.874 ns) + CELL(0.000 ns) 2.874 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 118 " "Info: 2: + IC(2.874 ns) + CELL(0.000 ns) = 2.874 ns; Loc. = CLKCTRL_G3; Fanout = 118; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.874 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.026 ns) + CELL(0.537 ns) 4.437 ns sld_hub:sld_hub_inst\|tdo 3 REG LCFF_X44_Y20_N11 2 " "Info: 3: + IC(1.026 ns) + CELL(0.537 ns) = 4.437 ns; Loc. = LCFF_X44_Y20_N11; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|tdo'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.563 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "../../../../../altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 321 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 12.10 % ) " "Info: Total cell delay = 0.537 ns ( 12.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.900 ns ( 87.90 % ) " "Info: Total interconnect delay = 3.900 ns ( 87.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.437 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.437 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|tdo {} } { 0.000ns 2.874ns 1.026ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 4.435 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 4.435 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.874 ns) + CELL(0.000 ns) 2.874 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 118 " "Info: 2: + IC(2.874 ns) + CELL(0.000 ns) = 2.874 ns; Loc. = CLKCTRL_G3; Fanout = 118; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.874 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.024 ns) + CELL(0.537 ns) 4.435 ns sld_hub:sld_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[4\] 3 REG LCFF_X40_Y20_N25 27 " "Info: 3: + IC(1.024 ns) + CELL(0.537 ns) = 4.435 ns; Loc. = LCFF_X40_Y20_N25; Fanout = 27; REG Node = 'sld_hub:sld_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[4\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.561 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] } "NODE_NAME" } } { "../../../../../altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 1002 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 12.11 % ) " "Info: Total cell delay = 0.537 ns ( 12.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.898 ns ( 87.89 % ) " "Info: Total interconnect delay = 3.898 ns ( 87.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.435 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.435 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] {} } { 0.000ns 2.874ns 1.024ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.437 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.437 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|tdo {} } { 0.000ns 2.874ns 1.026ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.435 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.435 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] {} } { 0.000ns 2.874ns 1.024ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "../../../../../altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 1002 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "../../../../../altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 321 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "../../../../../altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 1002 -1 0 } } { "../../../../../altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 321 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.425 ns" { sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] sld_hub:sld_hub_inst|tdo~423 sld_hub:sld_hub_inst|tdo~424 sld_hub:sld_hub_inst|tdo~426 sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.425 ns" { sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] {} sld_hub:sld_hub_inst|tdo~423 {} sld_hub:sld_hub_inst|tdo~424 {} sld_hub:sld_hub_inst|tdo~426 {} sld_hub:sld_hub_inst|tdo {} } { 0.000ns 0.757ns 0.251ns 0.264ns 0.000ns } { 0.000ns 0.416ns 0.275ns 0.378ns 0.084ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.437 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.437 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|tdo {} } { 0.000ns 2.874ns 1.026ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.435 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.435 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] {} } { 0.000ns 2.874ns 1.024ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram3\|ram_block4a0~porta_address_reg2 Wren CLK 6.656 ns memory " "Info: tsu for memory \"myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram3\|ram_block4a0~porta_address_reg2\" (data pin = \"Wren\", clock pin = \"CLK\") is 6.656 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.354 ns + Longest pin memory " "Info: + Longest pin to memory delay is 9.354 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns Wren 1 PIN PIN_W11 7 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_W11; Fanout = 7; PIN Node = 'Wren'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { Wren } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.669 ns) + CELL(0.415 ns) 7.934 ns Address_in\[1\]~221 2 COMB LCCOMB_X49_Y20_N14 1 " "Info: 2: + IC(6.669 ns) + CELL(0.415 ns) = 7.934 ns; Loc. = LCCOMB_X49_Y20_N14; Fanout = 1; COMB Node = 'Address_in\[1\]~221'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.084 ns" { Wren Address_in[1]~221 } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.278 ns) + CELL(0.142 ns) 9.354 ns myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram3\|ram_block4a0~porta_address_reg2 3 MEM M4K_X52_Y20 8 " "Info: 3: + IC(1.278 ns) + CELL(0.142 ns) = 9.354 ns; Loc. = M4K_X52_Y20; Fanout = 8; MEM Node = 'myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram3\|ram_block4a0~porta_address_reg2'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.420 ns" { Address_in[1]~221 myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 } "NODE_NAME" } } { "db/altsyncram_p592.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/db/altsyncram_p592.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.407 ns ( 15.04 % ) " "Info: Total cell delay = 1.407 ns ( 15.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.947 ns ( 84.96 % ) " "Info: Total interconnect delay = 7.947 ns ( 84.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "9.354 ns" { Wren Address_in[1]~221 myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "9.354 ns" { Wren {} Wren~combout {} Address_in[1]~221 {} myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 {} } { 0.000ns 0.000ns 6.669ns 1.278ns } { 0.000ns 0.850ns 0.415ns 0.142ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.035 ns + " "Info: + Micro setup delay of destination is 0.035 ns" {  } { { "db/altsyncram_p592.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/db/altsyncram_p592.tdf" 41 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.733 ns - Shortest memory " "Info: - Shortest clock path from clock \"CLK\" to destination memory is 2.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 2; CLK Node = 'CLK'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns CLK~clkctrl 2 COMB CLKCTRL_G2 47 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 47; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.960 ns) + CELL(0.661 ns) 2.733 ns myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram3\|ram_block4a0~porta_address_reg2 3 MEM M4K_X52_Y20 8 " "Info: 3: + IC(0.960 ns) + CELL(0.661 ns) = 2.733 ns; Loc. = M4K_X52_Y20; Fanout = 8; MEM Node = 'myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram3\|ram_block4a0~porta_address_reg2'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.621 ns" { CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 } "NODE_NAME" } } { "db/altsyncram_p592.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/db/altsyncram_p592.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 60.74 % ) " "Info: Total cell delay = 1.660 ns ( 60.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.073 ns ( 39.26 % ) " "Info: Total interconnect delay = 1.073 ns ( 39.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.733 ns" { CLK CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.733 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 {} } { 0.000ns 0.000ns 0.113ns 0.960ns } { 0.000ns 0.999ns 0.000ns 0.661ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "9.354 ns" { Wren Address_in[1]~221 myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "9.354 ns" { Wren {} Wren~combout {} Address_in[1]~221 {} myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 {} } { 0.000ns 0.000ns 6.669ns 1.278ns } { 0.000ns 0.850ns 0.415ns 0.142ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.733 ns" { CLK CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.733 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 {} } { 0.000ns 0.000ns 0.113ns 0.960ns } { 0.000ns 0.999ns 0.000ns 0.661ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK SEG_DATA\[3\] count:Cnt\|y.00010 19.214 ns register " "Info: tco from clock \"CLK\" to destination pin \"SEG_DATA\[3\]\" through register \"count:Cnt\|y.00010\" is 19.214 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 6.583 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 6.583 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 2; CLK Node = 'CLK'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.459 ns) + CELL(0.787 ns) 3.245 ns Clock 2 REG LCFF_X48_Y18_N1 2 " "Info: 2: + IC(1.459 ns) + CELL(0.787 ns) = 3.245 ns; Loc. = LCFF_X48_Y18_N1; Fanout = 2; REG Node = 'Clock'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.246 ns" { CLK Clock } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.799 ns) + CELL(0.000 ns) 5.044 ns Clock~clkctrl 3 COMB CLKCTRL_G6 32 " "Info: 3: + IC(1.799 ns) + CELL(0.000 ns) = 5.044 ns; Loc. = CLKCTRL_G6; Fanout = 32; COMB Node = 'Clock~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.799 ns" { Clock Clock~clkctrl } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.002 ns) + CELL(0.537 ns) 6.583 ns count:Cnt\|y.00010 4 REG LCFF_X50_Y20_N1 3 " "Info: 4: + IC(1.002 ns) + CELL(0.537 ns) = 6.583 ns; Loc. = LCFF_X50_Y20_N1; Fanout = 3; REG Node = 'count:Cnt\|y.00010'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.539 ns" { Clock~clkctrl count:Cnt|y.00010 } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 35.29 % ) " "Info: Total cell delay = 2.323 ns ( 35.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.260 ns ( 64.71 % ) " "Info: Total interconnect delay = 4.260 ns ( 64.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.583 ns" { CLK Clock Clock~clkctrl count:Cnt|y.00010 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "6.583 ns" { CLK {} CLK~combout {} Clock {} Clock~clkctrl {} count:Cnt|y.00010 {} } { 0.000ns 0.000ns 1.459ns 1.799ns 1.002ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 133 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.381 ns + Longest register pin " "Info: + Longest register to pin delay is 12.381 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count:Cnt\|y.00010 1 REG LCFF_X50_Y20_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X50_Y20_N1; Fanout = 3; REG Node = 'count:Cnt\|y.00010'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { count:Cnt|y.00010 } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.199 ns) + CELL(0.398 ns) 1.597 ns count:Cnt\|WideOr1~98 2 COMB LCCOMB_X50_Y20_N6 2 " "Info: 2: + IC(1.199 ns) + CELL(0.398 ns) = 1.597 ns; Loc. = LCCOMB_X50_Y20_N6; Fanout = 2; COMB Node = 'count:Cnt\|WideOr1~98'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.597 ns" { count:Cnt|y.00010 count:Cnt|WideOr1~98 } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 154 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.273 ns) + CELL(0.410 ns) 2.280 ns count:Cnt\|WideOr1~102 3 COMB LCCOMB_X50_Y20_N28 8 " "Info: 3: + IC(0.273 ns) + CELL(0.410 ns) = 2.280 ns; Loc. = LCCOMB_X50_Y20_N28; Fanout = 8; COMB Node = 'count:Cnt\|WideOr1~102'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.683 ns" { count:Cnt|WideOr1~98 count:Cnt|WideOr1~102 } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 154 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.895 ns) + CELL(0.275 ns) 4.450 ns display:D5\|out\[3\]~813 4 COMB LCCOMB_X42_Y12_N28 1 " "Info: 4: + IC(1.895 ns) + CELL(0.275 ns) = 4.450 ns; Loc. = LCCOMB_X42_Y12_N28; Fanout = 1; COMB Node = 'display:D5\|out\[3\]~813'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.170 ns" { count:Cnt|WideOr1~102 display:D5|out[3]~813 } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 160 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.478 ns) + CELL(0.419 ns) 5.347 ns SEG_DATA~3471 5 COMB LCCOMB_X43_Y12_N24 1 " "Info: 5: + IC(0.478 ns) + CELL(0.419 ns) = 5.347 ns; Loc. = LCCOMB_X43_Y12_N24; Fanout = 1; COMB Node = 'SEG_DATA~3471'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.897 ns" { display:D5|out[3]~813 SEG_DATA~3471 } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.261 ns) + CELL(0.275 ns) 5.883 ns SEG_DATA~3472 6 COMB LCCOMB_X43_Y12_N10 1 " "Info: 6: + IC(0.261 ns) + CELL(0.275 ns) = 5.883 ns; Loc. = LCCOMB_X43_Y12_N10; Fanout = 1; COMB Node = 'SEG_DATA~3472'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.536 ns" { SEG_DATA~3471 SEG_DATA~3472 } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.260 ns) + CELL(0.438 ns) 6.581 ns SEG_DATA~3473 7 COMB LCCOMB_X43_Y12_N12 1 " "Info: 7: + IC(0.260 ns) + CELL(0.438 ns) = 6.581 ns; Loc. = LCCOMB_X43_Y12_N12; Fanout = 1; COMB Node = 'SEG_DATA~3473'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.698 ns" { SEG_DATA~3472 SEG_DATA~3473 } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.002 ns) + CELL(2.798 ns) 12.381 ns SEG_DATA\[3\] 8 PIN PIN_AC6 0 " "Info: 8: + IC(3.002 ns) + CELL(2.798 ns) = 12.381 ns; Loc. = PIN_AC6; Fanout = 0; PIN Node = 'SEG_DATA\[3\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.800 ns" { SEG_DATA~3473 SEG_DATA[3] } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.013 ns ( 40.49 % ) " "Info: Total cell delay = 5.013 ns ( 40.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.368 ns ( 59.51 % ) " "Info: Total interconnect delay = 7.368 ns ( 59.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "12.381 ns" { count:Cnt|y.00010 count:Cnt|WideOr1~98 count:Cnt|WideOr1~102 display:D5|out[3]~813 SEG_DATA~3471 SEG_DATA~3472 SEG_DATA~3473 SEG_DATA[3] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "12.381 ns" { count:Cnt|y.00010 {} count:Cnt|WideOr1~98 {} count:Cnt|WideOr1~102 {} display:D5|out[3]~813 {} SEG_DATA~3471 {} SEG_DATA~3472 {} SEG_DATA~3473 {} SEG_DATA[3] {} } { 0.000ns 1.199ns 0.273ns 1.895ns 0.478ns 0.261ns 0.260ns 3.002ns } { 0.000ns 0.398ns 0.410ns 0.275ns 0.419ns 0.275ns 0.438ns 2.798ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.583 ns" { CLK Clock Clock~clkctrl count:Cnt|y.00010 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "6.583 ns" { CLK {} CLK~combout {} Clock {} Clock~clkctrl {} count:Cnt|y.00010 {} } { 0.000ns 0.000ns 1.459ns 1.799ns 1.002ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "12.381 ns" { count:Cnt|y.00010 count:Cnt|WideOr1~98 count:Cnt|WideOr1~102 display:D5|out[3]~813 SEG_DATA~3471 SEG_DATA~3472 SEG_DATA~3473 SEG_DATA[3] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "12.381 ns" { count:Cnt|y.00010 {} count:Cnt|WideOr1~98 {} count:Cnt|WideOr1~102 {} display:D5|out[3]~813 {} SEG_DATA~3471 {} SEG_DATA~3472 {} SEG_DATA~3473 {} SEG_DATA[3] {} } { 0.000ns 1.199ns 0.273ns 1.895ns 0.478ns 0.261ns 0.260ns 3.002ns } { 0.000ns 0.398ns 0.410ns 0.275ns 0.419ns 0.275ns 0.438ns 2.798ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}