part6.tan.qmsg

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 2 -1 0 } } { "c:/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "c:/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "Clock " "Info: Detected ripple clock \"Clock\" as buffer" {  } { { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 13 -1 0 } } { "c:/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "Clock" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register count:Cnt\|y.00100 memory myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram3\|ram_block4a0~porta_address_reg2 120.02 MHz 8.332 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 120.02 MHz between source register \"count:Cnt\|y.00100\" and destination memory \"myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram3\|ram_block4a0~porta_address_reg2\" (period= 8.332 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.197 ns + Longest register memory " "Info: + Longest register to memory delay is 4.197 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count:Cnt\|y.00100 1 REG LCFF_X50_Y20_N17 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X50_Y20_N17; Fanout = 3; REG Node = 'count:Cnt\|y.00100'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { count:Cnt|y.00100 } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.304 ns) + CELL(0.398 ns) 1.702 ns count:Cnt\|WideOr4~85 2 COMB LCCOMB_X49_Y20_N16 2 " "Info: 2: + IC(1.304 ns) + CELL(0.398 ns) = 1.702 ns; Loc. = LCCOMB_X49_Y20_N16; Fanout = 2; COMB Node = 'count:Cnt\|WideOr4~85'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.702 ns" { count:Cnt|y.00100 count:Cnt|WideOr4~85 } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 154 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.261 ns) + CELL(0.275 ns) 2.238 ns count:Cnt\|WideOr3~99 3 COMB LCCOMB_X49_Y20_N20 8 " "Info: 3: + IC(0.261 ns) + CELL(0.275 ns) = 2.238 ns; Loc. = LCCOMB_X49_Y20_N20; Fanout = 8; COMB Node = 'count:Cnt\|WideOr3~99'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.536 ns" { count:Cnt|WideOr4~85 count:Cnt|WideOr3~99 } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 154 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.268 ns) + CELL(0.271 ns) 2.777 ns Address_in\[1\]~221 4 COMB LCCOMB_X49_Y20_N14 1 " "Info: 4: + IC(0.268 ns) + CELL(0.271 ns) = 2.777 ns; Loc. = LCCOMB_X49_Y20_N14; Fanout = 1; COMB Node = 'Address_in\[1\]~221'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.539 ns" { count:Cnt|WideOr3~99 Address_in[1]~221 } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.278 ns) + CELL(0.142 ns) 4.197 ns myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram3\|ram_block4a0~porta_address_reg2 5 MEM M4K_X52_Y20 8 " "Info: 5: + IC(1.278 ns) + CELL(0.142 ns) = 4.197 ns; Loc. = M4K_X52_Y20; Fanout = 8; MEM Node = 'myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram3\|ram_block4a0~porta_address_reg2'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.420 ns" { Address_in[1]~221 myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 } "NODE_NAME" } } { "db/altsyncram_p592.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/db/altsyncram_p592.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.086 ns ( 25.88 % ) " "Info: Total cell delay = 1.086 ns ( 25.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.111 ns ( 74.12 % ) " "Info: Total interconnect delay = 3.111 ns ( 74.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.197 ns" { count:Cnt|y.00100 count:Cnt|WideOr4~85 count:Cnt|WideOr3~99 Address_in[1]~221 myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.197 ns" { count:Cnt|y.00100 {} count:Cnt|WideOr4~85 {} count:Cnt|WideOr3~99 {} Address_in[1]~221 {} myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 {} } { 0.000ns 1.304ns 0.261ns 0.268ns 1.278ns } { 0.000ns 0.398ns 0.275ns 0.271ns 0.142ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.850 ns - Smallest " "Info: - Smallest clock skew is -3.850 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.733 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLK\" to destination memory is 2.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 2; CLK Node = 'CLK'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns CLK~clkctrl 2 COMB CLKCTRL_G2 47 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 47; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.960 ns) + CELL(0.661 ns) 2.733 ns myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram3\|ram_block4a0~porta_address_reg2 3 MEM M4K_X52_Y20 8 " "Info: 3: + IC(0.960 ns) + CELL(0.661 ns) = 2.733 ns; Loc. = M4K_X52_Y20; Fanout = 8; MEM Node = 'myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram3\|ram_block4a0~porta_address_reg2'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.621 ns" { CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 } "NODE_NAME" } } { "db/altsyncram_p592.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/db/altsyncram_p592.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 60.74 % ) " "Info: Total cell delay = 1.660 ns ( 60.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.073 ns ( 39.26 % ) " "Info: Total interconnect delay = 1.073 ns ( 39.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.733 ns" { CLK CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.733 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 {} } { 0.000ns 0.000ns 0.113ns 0.960ns } { 0.000ns 0.999ns 0.000ns 0.661ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 6.583 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 6.583 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 2; CLK Node = 'CLK'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.459 ns) + CELL(0.787 ns) 3.245 ns Clock 2 REG LCFF_X48_Y18_N1 2 " "Info: 2: + IC(1.459 ns) + CELL(0.787 ns) = 3.245 ns; Loc. = LCFF_X48_Y18_N1; Fanout = 2; REG Node = 'Clock'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.246 ns" { CLK Clock } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.799 ns) + CELL(0.000 ns) 5.044 ns Clock~clkctrl 3 COMB CLKCTRL_G6 32 " "Info: 3: + IC(1.799 ns) + CELL(0.000 ns) = 5.044 ns; Loc. = CLKCTRL_G6; Fanout = 32; COMB Node = 'Clock~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.799 ns" { Clock Clock~clkctrl } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.002 ns) + CELL(0.537 ns) 6.583 ns count:Cnt\|y.00100 4 REG LCFF_X50_Y20_N17 3 " "Info: 4: + IC(1.002 ns) + CELL(0.537 ns) = 6.583 ns; Loc. = LCFF_X50_Y20_N17; Fanout = 3; REG Node = 'count:Cnt\|y.00100'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.539 ns" { Clock~clkctrl count:Cnt|y.00100 } "NODE_NAME" } } { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 35.29 % ) " "Info: Total cell delay = 2.323 ns ( 35.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.260 ns ( 64.71 % ) " "Info: Total interconnect delay = 4.260 ns ( 64.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.583 ns" { CLK Clock Clock~clkctrl count:Cnt|y.00100 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "6.583 ns" { CLK {} CLK~combout {} Clock {} Clock~clkctrl {} count:Cnt|y.00100 {} } { 0.000ns 0.000ns 1.459ns 1.799ns 1.002ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.733 ns" { CLK CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.733 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 {} } { 0.000ns 0.000ns 0.113ns 0.960ns } { 0.000ns 0.999ns 0.000ns 0.661ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.583 ns" { CLK Clock Clock~clkctrl count:Cnt|y.00100 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "6.583 ns" { CLK {} CLK~combout {} Clock {} Clock~clkctrl {} count:Cnt|y.00100 {} } { 0.000ns 0.000ns 1.459ns 1.799ns 1.002ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 133 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.035 ns + " "Info: + Micro setup delay of destination is 0.035 ns" {  } { { "db/altsyncram_p592.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/db/altsyncram_p592.tdf" 41 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.197 ns" { count:Cnt|y.00100 count:Cnt|WideOr4~85 count:Cnt|WideOr3~99 Address_in[1]~221 myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.197 ns" { count:Cnt|y.00100 {} count:Cnt|WideOr4~85 {} count:Cnt|WideOr3~99 {} Address_in[1]~221 {} myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 {} } { 0.000ns 1.304ns 0.261ns 0.268ns 1.278ns } { 0.000ns 0.398ns 0.275ns 0.271ns 0.142ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.733 ns" { CLK CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.733 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 {} } { 0.000ns 0.000ns 0.113ns 0.960ns } { 0.000ns 0.999ns 0.000ns 0.661ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.583 ns" { CLK Clock Clock~clkctrl count:Cnt|y.00100 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "6.583 ns" { CLK {} CLK~combout {} Clock {} Clock~clkctrl {} count:Cnt|y.00100 {} } { 0.000ns 0.000ns 1.459ns 1.799ns 1.002ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}