altsyncram_3af2.tdf

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

--altsyncram ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" CYCLONEII_SAFE_WRITE="RESTRUCTURE" DEVICE_FAMILY="Cyclone II" ENABLE_RUNTIME_MOD="NO" INDATA_ACLR_B="NONE" INDATA_REG_B="CLOCK1" INIT_FILE="part6.hex" LOW_POWER_MODE="AUTO" NUMWORDS_A=32 NUMWORDS_B=32 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="M4K" RDCONTROL_REG_B="CLOCK1" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=5 WIDTHAD_B=5 WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 data_a data_b q_a q_b wren_a wren_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 7.2SP2 cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:10:18:20:36:46:SJ cbx_stratixii 2007:10:19:15:30:42:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:11:07:17:40:20:SJ  VERSION_END


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FUNCTION altsyncram_g292 (address_a[5..0], address_b[5..0], clock0, clock1, data_a[7..0], data_b[7..0], wren_a, wren_b)
RETURNS ( q_a[7..0], q_b[7..0]);

--synthesis_resources = 
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altsyncram_3af2
( 
	address_a[4..0]	:	input;
	address_b[4..0]	:	input;
	clock0	:	input;
	clock1	:	input;
	data_a[7..0]	:	input;
	data_b[7..0]	:	input;
	q_a[7..0]	:	output;
	q_b[7..0]	:	output;
	wren_a	:	input;
	wren_b	:	input;
) 
VARIABLE 
	altsyncram1 : altsyncram_g292;

BEGIN 
	altsyncram1.address_a[] = ( address_a[4..0], B"0");
	altsyncram1.address_b[] = ( address_b[4..0], B"0");
	altsyncram1.clock0 = clock0;
	altsyncram1.clock1 = clock1;
	altsyncram1.data_a[] = data_a[];
	altsyncram1.data_b[] = data_b[];
	altsyncram1.wren_a = wren_a;
	altsyncram1.wren_b = wren_b;
	q_a[] = altsyncram1.q_a[];
	q_b[] = altsyncram1.q_b[];
END;
--VALID FILE