prev_cmp_part6.map.qmsg

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Web Edition " "Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 12 14:23:55 2008 " "Info: Processing started: Mon May 12 14:23:55 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part6 -c part6 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part6 -c part6" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "cnt Cnt part6.v(14) " "Info (10281): Verilog HDL Declaration information at part6.v(14): object \"cnt\" differs only in case from object \"Cnt\" in the same scope" {  } { { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 14 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "y Y part6.v(133) " "Info (10281): Verilog HDL Declaration information at part6.v(133): object \"y\" differs only in case from object \"Y\" in the same scope" {  } { { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 133 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part6.v 4 4 " "Info: Found 4 design units, including 4 entities, in source file part6.v" { { "Info" "ISGN_ENTITY_NAME" "1 part6 " "Info: Found entity 1: part6" {  } { { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 myram " "Info: Found entity 2: myram" {  } { { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 75 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "3 count " "Info: Found entity 3: count" {  } { { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 129 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "4 display " "Info: Found entity 4: display" {  } { { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 158 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "part6 " "Info: Elaborating entity \"part6\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 part6.v(19) " "Warning (10230): Verilog HDL assignment warning at part6.v(19): truncated value with size 32 to match size of target (3)" {  } { { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 19 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 part6.v(20) " "Warning (10230): Verilog HDL assignment warning at part6.v(20): truncated value with size 32 to match size of target (11)" {  } { { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 20 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 part6.v(22) " "Warning (10230): Verilog HDL assignment warning at part6.v(22): truncated value with size 32 to match size of target (11)" {  } { { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 22 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 part6.v(25) " "Warning (10230): Verilog HDL assignment warning at part6.v(25): truncated value with size 32 to match size of target (1)" {  } { { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 25 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Count_v part6.v(36) " "Warning (10235): Verilog HDL Always Construct warning at part6.v(36): variable \"Count_v\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 36 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "count count:Cnt " "Info: Elaborating entity \"count\" for hierarchy \"count:Cnt\"" {  } { { "part6.v" "Cnt" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 41 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "myram myram:Ram " "Info: Elaborating entity \"myram\" for hierarchy \"myram:Ram\"" {  } { { "part6.v" "Ram" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 42 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/72sp2/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram myram:Ram\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"myram:Ram\|altsyncram:altsyncram_component\"" {  } { { "part6.v" "altsyncram_component" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 108 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}