altsyncram_irj1.tdf

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

--altsyncram CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" CYCLONEII_SAFE_WRITE="RESTRUCTURE" DEVICE_FAMILY="Cyclone II" ENABLE_RUNTIME_MOD="YES" INIT_FILE="myram.mif" INSTANCE_NAME="32*8" LOW_POWER_MODE="AUTO" NUMWORDS_A=32 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="M4K" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=5 address_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 7.0 cbx_altsyncram 2007:01:25:14:36:16:SJ cbx_cycloneii 2006:09:29:19:03:26:SJ cbx_lpm_add_sub 2006:10:10:22:03:24:SJ cbx_lpm_compare 2006:04:25:14:54:12:SJ cbx_lpm_decode 2006:04:25:15:10:18:SJ cbx_lpm_mux 2006:04:25:15:10:08:SJ cbx_mgl 2006:10:27:16:08:48:SJ cbx_stratix 2006:09:18:10:47:42:SJ cbx_stratixii 2006:10:13:14:01:30:SJ cbx_stratixiii 2006:10:19:19:28:28:SJ cbx_util_mgl 2006:11:03:10:32:30:SJ  VERSION_END


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FUNCTION altsyncram_jbf2 (address_a[4..0], address_b[4..0], clock0, clock1, data_a[7..0], data_b[7..0], wren_a, wren_b)
RETURNS ( q_a[7..0], q_b[7..0]);
FUNCTION sld_mod_ram_rom (data_read[7..0])
WITH ( 	CVALUE,	IS_DATA_IN_RAM,	IS_READABLE,	NODE_NAME,	NUMWORDS,	SHIFT_COUNT_BITS,	WIDTH_WORD,	WIDTHAD) 
RETURNS ( address[4..0], data_write[7..0], enable_write, tck_usr);

--synthesis_resources = M4K 1 sld_mod_ram_rom 1 
SUBDESIGN altsyncram_irj1
( 
	address_a[4..0]	:	input;
	clock0	:	input;
	data_a[7..0]	:	input;
	q_a[7..0]	:	output;
	wren_a	:	input;
) 
VARIABLE 
	altsyncram1 : altsyncram_jbf2;
	mgl_prim2 : sld_mod_ram_rom
		WITH (
			CVALUE = "00000000",
			IS_DATA_IN_RAM = 1,
			IS_READABLE = 1,
			NODE_NAME = 858925624,
			NUMWORDS = 32,
			SHIFT_COUNT_BITS = 4,
			WIDTH_WORD = 8,
			WIDTHAD = 5
		);

BEGIN 
	altsyncram1.address_a[] = address_a[];
	altsyncram1.address_b[] = mgl_prim2.address[];
	altsyncram1.clock0 = clock0;
	altsyncram1.clock1 = mgl_prim2.tck_usr;
	altsyncram1.data_a[] = data_a[];
	altsyncram1.data_b[] = mgl_prim2.data_write[];
	altsyncram1.wren_a = wren_a;
	altsyncram1.wren_b = mgl_prim2.enable_write;
	mgl_prim2.data_read[] = altsyncram1.q_b[];
	q_a[] = altsyncram1.q_a[];
END;
--VALID FILE