prev_cmp_part6.eda.qmsg

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Web Edition " "Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 12 14:24:58 2008 " "Info: Processing started: Mon May 12 14:24:58 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off part6 -c part6 " "Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off part6 -c part6" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IWSC_DONE_HDL_SDO_GENERATION" "part6.vo part6_v.sdo C:/altera/72sp2/LAB8/part6/simulation/modelsim/ simulation " "Info: Generated files \"part6.vo\" and \"part6_v.sdo\" in directory \"C:/altera/72sp2/LAB8/part6/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 0 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0 "" 0}
{ "Info" "IWSC_DONE_HDL_SDO_GENERATION" "part6.vo part6_v.sdo C:/altera/72sp2/LAB8/part6/timing/primetime/ timing analysis " "Info: Generated files \"part6.vo\" and \"part6_v.sdo\" in directory \"C:/altera/72sp2/LAB8/part6/timing/primetime/\" for EDA timing analysis tool" {  } {  } 0 0 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0 "" 0}
{ "Warning" "WPTO_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Expected ENABLE_CLOCK_LATENCY to be set to ON but is set to OFF" {  } {  } 0 0 "Expected ENABLE_CLOCK_LATENCY to be set to ON but is set to OFF" 0 0 "" 0}
{ "Info" "IPTO_FILE_GENERATED_MSG" "PrimeTime Tcl script file C:/altera/72sp2/LAB8/part6/timing/primetime/part6_pt_v.tcl " "Info: Generated PrimeTime Tcl script file C:/altera/72sp2/LAB8/part6/timing/primetime/part6_pt_v.tcl" {  } {  } 0 0 "Generated %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  Quartus II " "Info: Quartus II EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "147 " "Info: Allocated 147 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 12 14:25:00 2008 " "Info: Processing ended: Mon May 12 14:25:00 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}