prev_cmp_part6.fit.qmsg

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.971 ns register memory " "Info: Estimated most critical path is register to memory delay of 3.971 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count:Cnt\|y.01110 1 REG LAB_X51_Y17 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X51_Y17; Fanout = 3; REG Node = 'count:Cnt\|y.01110'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { count:Cnt|y.01110 } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.807 ns) + CELL(0.275 ns) 1.082 ns count:Cnt\|WideOr4~98 2 COMB LAB_X49_Y17 1 " "Info: 2: + IC(0.807 ns) + CELL(0.275 ns) = 1.082 ns; Loc. = LAB_X49_Y17; Fanout = 1; COMB Node = 'count:Cnt\|WideOr4~98'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.082 ns" { count:Cnt|y.01110 count:Cnt|WideOr4~98 } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 154 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.150 ns) 1.647 ns count:Cnt\|WideOr4~99 3 COMB LAB_X49_Y17 8 " "Info: 3: + IC(0.415 ns) + CELL(0.150 ns) = 1.647 ns; Loc. = LAB_X49_Y17; Fanout = 8; COMB Node = 'count:Cnt\|WideOr4~99'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.565 ns" { count:Cnt|WideOr4~98 count:Cnt|WideOr4~99 } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 154 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.150 ns) 2.212 ns Address_in\[0\]~220 4 COMB LAB_X49_Y17 8 " "Info: 4: + IC(0.415 ns) + CELL(0.150 ns) = 2.212 ns; Loc. = LAB_X49_Y17; Fanout = 8; COMB Node = 'Address_in\[0\]~220'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.565 ns" { count:Cnt|WideOr4~99 Address_in[0]~220 } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.617 ns) + CELL(0.142 ns) 3.971 ns myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram1\|ram_block4a6~porta_address_reg1 5 MEM M4K_X26_Y15 1 " "Info: 5: + IC(1.617 ns) + CELL(0.142 ns) = 3.971 ns; Loc. = M4K_X26_Y15; Fanout = 1; MEM Node = 'myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram1\|ram_block4a6~porta_address_reg1'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.759 ns" { Address_in[0]~220 myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a6~porta_address_reg1 } "NODE_NAME" } } { "db/altsyncram_p592.tdf" "" { Text "C:/altera/72sp2/LAB8/part6/db/altsyncram_p592.tdf" 233 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.717 ns ( 18.06 % ) " "Info: Total cell delay = 0.717 ns ( 18.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.254 ns ( 81.94 % ) " "Info: Total interconnect delay = 3.254 ns ( 81.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.971 ns" { count:Cnt|y.01110 count:Cnt|WideOr4~98 count:Cnt|WideOr4~99 Address_in[0]~220 myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a6~porta_address_reg1 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X22_Y12 X32_Y23 " "Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X22_Y12 to location X32_Y23" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}