prev_cmp_part6.fit.qmsg

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK (placed in PIN N1 (CLK1, LVDSCLK0n, Input)) " "Info: Automatically promoted node CLK (placed in PIN N1 (CLK1, LVDSCLK0n, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Clock " "Info: Destination node Clock" {  } { { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 13 -1 0 } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72sp2/quartus/bin/pin_planner.ppl" { CLK } } } { "c:/altera/72sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 2 -1 0 } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Info: Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "Clock  " "Info: Automatically promoted node Clock " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Clock~18 " "Info: Destination node Clock~18" {  } { { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 13 -1 0 } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clock~18 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clock~18 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 13 -1 0 } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|CLR_SIGNAL  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|CLR_SIGNAL " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|CLR_SIGNAL~_wirecell " "Info: Destination node sld_hub:sld_hub_inst\|CLR_SIGNAL~_wirecell" {  } { { "../../quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL~_wirecell } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL~_wirecell } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "../../quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } } { "c:/altera/72sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|CLR_SIGNAL" } } } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~442 " "Info: Destination node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~442" {  } { { "../../quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_hub.vhd" 1148 -1 0 } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~442 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~442 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5 " "Info: Destination node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5" {  } { { "../../quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_hub.vhd" 1148 -1 0 } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]~_wirecell " "Info: Destination node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]~_wirecell" {  } { { "../../quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_hub.vhd" 1163 -1 0 } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]~_wirecell } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]~_wirecell } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "../../quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_hub.vhd" 1163 -1 0 } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|tdo~195 " "Info: Destination node myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|tdo~195" {  } { { "../../quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 65 -1 0 } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|tdo~195 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|tdo~195 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg~6 " "Info: Destination node myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg~6" {  } { { "../../quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 704 -1 0 } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg~6 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg~6 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0 " "Info: Destination node myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "../../quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0  " "Info: Automatically promoted node myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\]  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~11 " "Info: Destination node myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~11" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~11 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~11 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process1~1 " "Info: Destination node myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process1~1" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|process1~1 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|process1~1 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process0~9 " "Info: Destination node myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process0~9" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|process0~9 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|process0~9 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "../../quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|CLR_SIGNAL~_wirecell  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|CLR_SIGNAL~_wirecell " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "../../quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL~_wirecell } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL~_wirecell } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 0 0 "" 0}