prev_cmp_part6.tan.qmsg

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 register sld_hub:sld_hub_inst\|hub_tdo_reg 197.16 MHz 5.072 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 197.16 MHz between source register \"sld_hub:sld_hub_inst\|jtag_debug_mode_usr1\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo_reg\" (period= 5.072 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.328 ns + Longest register register " "Info: + Longest register to register delay is 2.328 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 1 REG LCFF_X23_Y14_N1 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X23_Y14_N1; Fanout = 18; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "../../quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_hub.vhd" 393 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.792 ns) + CELL(0.398 ns) 1.190 ns sld_hub:sld_hub_inst\|hub_tdo_reg~292 2 COMB LCCOMB_X24_Y15_N6 1 " "Info: 2: + IC(0.792 ns) + CELL(0.398 ns) = 1.190 ns; Loc. = LCCOMB_X24_Y15_N6; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~292'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.190 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo_reg~292 } "NODE_NAME" } } { "../../quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.243 ns) + CELL(0.150 ns) 1.583 ns sld_hub:sld_hub_inst\|hub_tdo_reg~293 3 COMB LCCOMB_X24_Y15_N10 1 " "Info: 3: + IC(0.243 ns) + CELL(0.150 ns) = 1.583 ns; Loc. = LCCOMB_X24_Y15_N10; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~293'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.393 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~292 sld_hub:sld_hub_inst|hub_tdo_reg~293 } "NODE_NAME" } } { "../../quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.263 ns) + CELL(0.398 ns) 2.244 ns sld_hub:sld_hub_inst\|hub_tdo_reg~295 4 COMB LCCOMB_X24_Y15_N4 1 " "Info: 4: + IC(0.263 ns) + CELL(0.398 ns) = 2.244 ns; Loc. = LCCOMB_X24_Y15_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~295'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.661 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~293 sld_hub:sld_hub_inst|hub_tdo_reg~295 } "NODE_NAME" } } { "../../quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.328 ns sld_hub:sld_hub_inst\|hub_tdo_reg 5 REG LCFF_X24_Y15_N5 2 " "Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 2.328 ns; Loc. = LCFF_X24_Y15_N5; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "../../quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.030 ns ( 44.24 % ) " "Info: Total cell delay = 1.030 ns ( 44.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.298 ns ( 55.76 % ) " "Info: Total interconnect delay = 1.298 ns ( 55.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.328 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo_reg~292 sld_hub:sld_hub_inst|hub_tdo_reg~293 sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "2.328 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 {} sld_hub:sld_hub_inst|hub_tdo_reg~292 {} sld_hub:sld_hub_inst|hub_tdo_reg~293 {} sld_hub:sld_hub_inst|hub_tdo_reg~295 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 0.792ns 0.243ns 0.263ns 0.000ns } { 0.000ns 0.398ns 0.150ns 0.398ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.006 ns - Smallest " "Info: - Smallest clock skew is 0.006 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.456 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 4.456 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.888 ns) + CELL(0.000 ns) 2.888 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 125 " "Info: 2: + IC(2.888 ns) + CELL(0.000 ns) = 2.888 ns; Loc. = CLKCTRL_G3; Fanout = 125; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.888 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.537 ns) 4.456 ns sld_hub:sld_hub_inst\|hub_tdo_reg 3 REG LCFF_X24_Y15_N5 2 " "Info: 3: + IC(1.031 ns) + CELL(0.537 ns) = 4.456 ns; Loc. = LCFF_X24_Y15_N5; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "../../quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 12.05 % ) " "Info: Total cell delay = 0.537 ns ( 12.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.919 ns ( 87.95 % ) " "Info: Total interconnect delay = 3.919 ns ( 87.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.456 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "4.456 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 2.888ns 1.031ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 4.450 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 4.450 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.888 ns) + CELL(0.000 ns) 2.888 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 125 " "Info: 2: + IC(2.888 ns) + CELL(0.000 ns) = 2.888 ns; Loc. = CLKCTRL_G3; Fanout = 125; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.888 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.025 ns) + CELL(0.537 ns) 4.450 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 3 REG LCFF_X23_Y14_N1 18 " "Info: 3: + IC(1.025 ns) + CELL(0.537 ns) = 4.450 ns; Loc. = LCFF_X23_Y14_N1; Fanout = 18; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.562 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "../../quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_hub.vhd" 393 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 12.07 % ) " "Info: Total cell delay = 0.537 ns ( 12.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.913 ns ( 87.93 % ) " "Info: Total interconnect delay = 3.913 ns ( 87.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.450 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "4.450 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|jtag_debug_mode_usr1 {} } { 0.000ns 2.888ns 1.025ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.456 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "4.456 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 2.888ns 1.031ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.450 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "4.450 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|jtag_debug_mode_usr1 {} } { 0.000ns 2.888ns 1.025ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "../../quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_hub.vhd" 393 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "../../quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "../../quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_hub.vhd" 393 -1 0 } } { "../../quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72sp2/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.328 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo_reg~292 sld_hub:sld_hub_inst|hub_tdo_reg~293 sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "2.328 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 {} sld_hub:sld_hub_inst|hub_tdo_reg~292 {} sld_hub:sld_hub_inst|hub_tdo_reg~293 {} sld_hub:sld_hub_inst|hub_tdo_reg~295 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 0.792ns 0.243ns 0.263ns 0.000ns } { 0.000ns 0.398ns 0.150ns 0.398ns 0.084ns } "" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.456 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "4.456 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 2.888ns 1.031ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.450 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "4.450 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|jtag_debug_mode_usr1 {} } { 0.000ns 2.888ns 1.025ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram1\|ram_block4a0~porta_address_reg5 Wren CLK 6.925 ns memory " "Info: tsu for memory \"myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram1\|ram_block4a0~porta_address_reg5\" (data pin = \"Wren\", clock pin = \"CLK\") is 6.925 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.633 ns + Longest pin memory " "Info: + Longest pin to memory delay is 9.633 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns Wren 1 PIN PIN_W11 7 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_W11; Fanout = 7; PIN Node = 'Wren'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Wren } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.591 ns) + CELL(0.419 ns) 7.860 ns Address_in\[4\]~224 2 COMB LCCOMB_X50_Y17_N2 1 " "Info: 2: + IC(6.591 ns) + CELL(0.419 ns) = 7.860 ns; Loc. = LCCOMB_X50_Y17_N2; Fanout = 1; COMB Node = 'Address_in\[4\]~224'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.010 ns" { Wren Address_in[4]~224 } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.631 ns) + CELL(0.142 ns) 9.633 ns myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram1\|ram_block4a0~porta_address_reg5 3 MEM M4K_X26_Y15 8 " "Info: 3: + IC(1.631 ns) + CELL(0.142 ns) = 9.633 ns; Loc. = M4K_X26_Y15; Fanout = 8; MEM Node = 'myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram1\|ram_block4a0~porta_address_reg5'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.773 ns" { Address_in[4]~224 myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 } "NODE_NAME" } } { "db/altsyncram_p592.tdf" "" { Text "C:/altera/72sp2/LAB8/part6/db/altsyncram_p592.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.411 ns ( 14.65 % ) " "Info: Total cell delay = 1.411 ns ( 14.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.222 ns ( 85.35 % ) " "Info: Total interconnect delay = 8.222 ns ( 85.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.633 ns" { Wren Address_in[4]~224 myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "9.633 ns" { Wren {} Wren~combout {} Address_in[4]~224 {} myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 {} } { 0.000ns 0.000ns 6.591ns 1.631ns } { 0.000ns 0.850ns 0.419ns 0.142ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.035 ns + " "Info: + Micro setup delay of destination is 0.035 ns" {  } { { "db/altsyncram_p592.tdf" "" { Text "C:/altera/72sp2/LAB8/part6/db/altsyncram_p592.tdf" 41 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.743 ns - Shortest memory " "Info: - Shortest clock path from clock \"CLK\" to destination memory is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 2; CLK Node = 'CLK'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns CLK~clkctrl 2 COMB CLKCTRL_G2 47 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 47; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.970 ns) + CELL(0.661 ns) 2.743 ns myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram1\|ram_block4a0~porta_address_reg5 3 MEM M4K_X26_Y15 8 " "Info: 3: + IC(0.970 ns) + CELL(0.661 ns) = 2.743 ns; Loc. = M4K_X26_Y15; Fanout = 8; MEM Node = 'myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram1\|ram_block4a0~porta_address_reg5'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.631 ns" { CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 } "NODE_NAME" } } { "db/altsyncram_p592.tdf" "" { Text "C:/altera/72sp2/LAB8/part6/db/altsyncram_p592.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 60.52 % ) " "Info: Total cell delay = 1.660 ns ( 60.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.083 ns ( 39.48 % ) " "Info: Total interconnect delay = 1.083 ns ( 39.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { CLK CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 {} } { 0.000ns 0.000ns 0.113ns 0.970ns } { 0.000ns 0.999ns 0.000ns 0.661ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.633 ns" { Wren Address_in[4]~224 myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "9.633 ns" { Wren {} Wren~combout {} Address_in[4]~224 {} myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 {} } { 0.000ns 0.000ns 6.591ns 1.631ns } { 0.000ns 0.850ns 0.419ns 0.142ns } "" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { CLK CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 {} } { 0.000ns 0.000ns 0.113ns 0.970ns } { 0.000ns 0.999ns 0.000ns 0.661ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK SEG_DATA\[1\] count:Cnt\|y.00000 18.976 ns register " "Info: tco from clock \"CLK\" to destination pin \"SEG_DATA\[1\]\" through register \"count:Cnt\|y.00000\" is 18.976 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.994 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 5.994 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 2; CLK Node = 'CLK'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.787 ns) 2.830 ns Clock 2 REG LCFF_X18_Y20_N25 2 " "Info: 2: + IC(1.044 ns) + CELL(0.787 ns) = 2.830 ns; Loc. = LCFF_X18_Y20_N25; Fanout = 2; REG Node = 'Clock'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.831 ns" { CLK Clock } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.596 ns) + CELL(0.000 ns) 4.426 ns Clock~clkctrl 3 COMB CLKCTRL_G0 32 " "Info: 3: + IC(1.596 ns) + CELL(0.000 ns) = 4.426 ns; Loc. = CLKCTRL_G0; Fanout = 32; COMB Node = 'Clock~clkctrl'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.596 ns" { Clock Clock~clkctrl } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.537 ns) 5.994 ns count:Cnt\|y.00000 4 REG LCFF_X49_Y17_N17 3 " "Info: 4: + IC(1.031 ns) + CELL(0.537 ns) = 5.994 ns; Loc. = LCFF_X49_Y17_N17; Fanout = 3; REG Node = 'count:Cnt\|y.00000'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { Clock~clkctrl count:Cnt|y.00000 } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 38.76 % ) " "Info: Total cell delay = 2.323 ns ( 38.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.671 ns ( 61.24 % ) " "Info: Total interconnect delay = 3.671 ns ( 61.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.994 ns" { CLK Clock Clock~clkctrl count:Cnt|y.00000 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "5.994 ns" { CLK {} CLK~combout {} Clock {} Clock~clkctrl {} count:Cnt|y.00000 {} } { 0.000ns 0.000ns 1.044ns 1.596ns 1.031ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 133 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.732 ns + Longest register pin " "Info: + Longest register to pin delay is 12.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count:Cnt\|y.00000 1 REG LCFF_X49_Y17_N17 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X49_Y17_N17; Fanout = 3; REG Node = 'count:Cnt\|y.00000'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { count:Cnt|y.00000 } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.770 ns) + CELL(0.150 ns) 0.920 ns count:Cnt\|WideOr1~109 2 COMB LCCOMB_X50_Y17_N16 2 " "Info: 2: + IC(0.770 ns) + CELL(0.150 ns) = 0.920 ns; Loc. = LCCOMB_X50_Y17_N16; Fanout = 2; COMB Node = 'count:Cnt\|WideOr1~109'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.920 ns" { count:Cnt|y.00000 count:Cnt|WideOr1~109 } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 154 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.703 ns) + CELL(0.275 ns) 1.898 ns count:Cnt\|WideOr1~113 3 COMB LCCOMB_X50_Y17_N0 8 " "Info: 3: + IC(0.703 ns) + CELL(0.275 ns) = 1.898 ns; Loc. = LCCOMB_X50_Y17_N0; Fanout = 8; COMB Node = 'count:Cnt\|WideOr1~113'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.978 ns" { count:Cnt|WideOr1~109 count:Cnt|WideOr1~113 } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 154 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.190 ns) + CELL(0.150 ns) 5.238 ns SEG_DATA~3363 4 COMB LCCOMB_X25_Y12_N12 1 " "Info: 4: + IC(3.190 ns) + CELL(0.150 ns) = 5.238 ns; Loc. = LCCOMB_X25_Y12_N12; Fanout = 1; COMB Node = 'SEG_DATA~3363'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.340 ns" { count:Cnt|WideOr1~113 SEG_DATA~3363 } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.267 ns) + CELL(0.438 ns) 5.943 ns SEG_DATA~3398 5 COMB LCCOMB_X25_Y12_N14 1 " "Info: 5: + IC(0.267 ns) + CELL(0.438 ns) = 5.943 ns; Loc. = LCCOMB_X25_Y12_N14; Fanout = 1; COMB Node = 'SEG_DATA~3398'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.705 ns" { SEG_DATA~3363 SEG_DATA~3398 } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.639 ns) + CELL(0.438 ns) 7.020 ns SEG_DATA~3399 6 COMB LCCOMB_X22_Y12_N12 1 " "Info: 6: + IC(0.639 ns) + CELL(0.438 ns) = 7.020 ns; Loc. = LCCOMB_X22_Y12_N12; Fanout = 1; COMB Node = 'SEG_DATA~3399'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.077 ns" { SEG_DATA~3398 SEG_DATA~3399 } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.269 ns) + CELL(0.438 ns) 7.727 ns SEG_DATA~3364 7 COMB LCCOMB_X22_Y12_N20 1 " "Info: 7: + IC(0.269 ns) + CELL(0.438 ns) = 7.727 ns; Loc. = LCCOMB_X22_Y12_N20; Fanout = 1; COMB Node = 'SEG_DATA~3364'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.707 ns" { SEG_DATA~3399 SEG_DATA~3364 } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.187 ns) + CELL(2.818 ns) 12.732 ns SEG_DATA\[1\] 8 PIN PIN_AE5 0 " "Info: 8: + IC(2.187 ns) + CELL(2.818 ns) = 12.732 ns; Loc. = PIN_AE5; Fanout = 0; PIN Node = 'SEG_DATA\[1\]'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.005 ns" { SEG_DATA~3364 SEG_DATA[1] } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.707 ns ( 36.97 % ) " "Info: Total cell delay = 4.707 ns ( 36.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.025 ns ( 63.03 % ) " "Info: Total interconnect delay = 8.025 ns ( 63.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "12.732 ns" { count:Cnt|y.00000 count:Cnt|WideOr1~109 count:Cnt|WideOr1~113 SEG_DATA~3363 SEG_DATA~3398 SEG_DATA~3399 SEG_DATA~3364 SEG_DATA[1] } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "12.732 ns" { count:Cnt|y.00000 {} count:Cnt|WideOr1~109 {} count:Cnt|WideOr1~113 {} SEG_DATA~3363 {} SEG_DATA~3398 {} SEG_DATA~3399 {} SEG_DATA~3364 {} SEG_DATA[1] {} } { 0.000ns 0.770ns 0.703ns 3.190ns 0.267ns 0.639ns 0.269ns 2.187ns } { 0.000ns 0.150ns 0.275ns 0.150ns 0.438ns 0.438ns 0.438ns 2.818ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.994 ns" { CLK Clock Clock~clkctrl count:Cnt|y.00000 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "5.994 ns" { CLK {} CLK~combout {} Clock {} Clock~clkctrl {} count:Cnt|y.00000 {} } { 0.000ns 0.000ns 1.044ns 1.596ns 1.031ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "12.732 ns" { count:Cnt|y.00000 count:Cnt|WideOr1~109 count:Cnt|WideOr1~113 SEG_DATA~3363 SEG_DATA~3398 SEG_DATA~3399 SEG_DATA~3364 SEG_DATA[1] } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "12.732 ns" { count:Cnt|y.00000 {} count:Cnt|WideOr1~109 {} count:Cnt|WideOr1~113 {} SEG_DATA~3363 {} SEG_DATA~3398 {} SEG_DATA~3399 {} SEG_DATA~3364 {} SEG_DATA[1] {} } { 0.000ns 0.770ns 0.703ns 3.190ns 0.267ns 0.639ns 0.269ns 2.187ns } { 0.000ns 0.150ns 0.275ns 0.150ns 0.438ns 0.438ns 0.438ns 2.818ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}