prev_cmp_part6.tan.qmsg

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 2 -1 0 } } { "c:/altera/72sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "c:/altera/72sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "Clock " "Info: Detected ripple clock \"Clock\" as buffer" {  } { { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 13 -1 0 } } { "c:/altera/72sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "Clock" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register count:Cnt\|y.00000 memory myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram1\|ram_block4a0~porta_address_reg5 130.14 MHz 7.684 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 130.14 MHz between source register \"count:Cnt\|y.00000\" and destination memory \"myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram1\|ram_block4a0~porta_address_reg5\" (period= 7.684 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.148 ns + Longest register memory " "Info: + Longest register to memory delay is 4.148 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count:Cnt\|y.00000 1 REG LCFF_X49_Y17_N17 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X49_Y17_N17; Fanout = 3; REG Node = 'count:Cnt\|y.00000'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { count:Cnt|y.00000 } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.770 ns) + CELL(0.150 ns) 0.920 ns count:Cnt\|WideOr1~109 2 COMB LCCOMB_X50_Y17_N16 2 " "Info: 2: + IC(0.770 ns) + CELL(0.150 ns) = 0.920 ns; Loc. = LCCOMB_X50_Y17_N16; Fanout = 2; COMB Node = 'count:Cnt\|WideOr1~109'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.920 ns" { count:Cnt|y.00000 count:Cnt|WideOr1~109 } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 154 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.460 ns) + CELL(0.393 ns) 1.773 ns count:Cnt\|WideOr0~64 3 COMB LCCOMB_X50_Y17_N8 4 " "Info: 3: + IC(0.460 ns) + CELL(0.393 ns) = 1.773 ns; Loc. = LCCOMB_X50_Y17_N8; Fanout = 4; COMB Node = 'count:Cnt\|WideOr0~64'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.853 ns" { count:Cnt|WideOr1~109 count:Cnt|WideOr0~64 } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 154 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.150 ns) 2.375 ns Address_in\[4\]~224 4 COMB LCCOMB_X50_Y17_N2 1 " "Info: 4: + IC(0.452 ns) + CELL(0.150 ns) = 2.375 ns; Loc. = LCCOMB_X50_Y17_N2; Fanout = 1; COMB Node = 'Address_in\[4\]~224'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.602 ns" { count:Cnt|WideOr0~64 Address_in[4]~224 } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.631 ns) + CELL(0.142 ns) 4.148 ns myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram1\|ram_block4a0~porta_address_reg5 5 MEM M4K_X26_Y15 8 " "Info: 5: + IC(1.631 ns) + CELL(0.142 ns) = 4.148 ns; Loc. = M4K_X26_Y15; Fanout = 8; MEM Node = 'myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram1\|ram_block4a0~porta_address_reg5'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.773 ns" { Address_in[4]~224 myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 } "NODE_NAME" } } { "db/altsyncram_p592.tdf" "" { Text "C:/altera/72sp2/LAB8/part6/db/altsyncram_p592.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.835 ns ( 20.13 % ) " "Info: Total cell delay = 0.835 ns ( 20.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.313 ns ( 79.87 % ) " "Info: Total interconnect delay = 3.313 ns ( 79.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.148 ns" { count:Cnt|y.00000 count:Cnt|WideOr1~109 count:Cnt|WideOr0~64 Address_in[4]~224 myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "4.148 ns" { count:Cnt|y.00000 {} count:Cnt|WideOr1~109 {} count:Cnt|WideOr0~64 {} Address_in[4]~224 {} myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 {} } { 0.000ns 0.770ns 0.460ns 0.452ns 1.631ns } { 0.000ns 0.150ns 0.393ns 0.150ns 0.142ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.251 ns - Smallest " "Info: - Smallest clock skew is -3.251 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.743 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLK\" to destination memory is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 2; CLK Node = 'CLK'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns CLK~clkctrl 2 COMB CLKCTRL_G2 47 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 47; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.970 ns) + CELL(0.661 ns) 2.743 ns myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram1\|ram_block4a0~porta_address_reg5 3 MEM M4K_X26_Y15 8 " "Info: 3: + IC(0.970 ns) + CELL(0.661 ns) = 2.743 ns; Loc. = M4K_X26_Y15; Fanout = 8; MEM Node = 'myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram1\|ram_block4a0~porta_address_reg5'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.631 ns" { CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 } "NODE_NAME" } } { "db/altsyncram_p592.tdf" "" { Text "C:/altera/72sp2/LAB8/part6/db/altsyncram_p592.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 60.52 % ) " "Info: Total cell delay = 1.660 ns ( 60.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.083 ns ( 39.48 % ) " "Info: Total interconnect delay = 1.083 ns ( 39.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { CLK CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 {} } { 0.000ns 0.000ns 0.113ns 0.970ns } { 0.000ns 0.999ns 0.000ns 0.661ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.994 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 5.994 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 2; CLK Node = 'CLK'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.787 ns) 2.830 ns Clock 2 REG LCFF_X18_Y20_N25 2 " "Info: 2: + IC(1.044 ns) + CELL(0.787 ns) = 2.830 ns; Loc. = LCFF_X18_Y20_N25; Fanout = 2; REG Node = 'Clock'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.831 ns" { CLK Clock } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.596 ns) + CELL(0.000 ns) 4.426 ns Clock~clkctrl 3 COMB CLKCTRL_G0 32 " "Info: 3: + IC(1.596 ns) + CELL(0.000 ns) = 4.426 ns; Loc. = CLKCTRL_G0; Fanout = 32; COMB Node = 'Clock~clkctrl'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.596 ns" { Clock Clock~clkctrl } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.537 ns) 5.994 ns count:Cnt\|y.00000 4 REG LCFF_X49_Y17_N17 3 " "Info: 4: + IC(1.031 ns) + CELL(0.537 ns) = 5.994 ns; Loc. = LCFF_X49_Y17_N17; Fanout = 3; REG Node = 'count:Cnt\|y.00000'" {  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { Clock~clkctrl count:Cnt|y.00000 } "NODE_NAME" } } { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 38.76 % ) " "Info: Total cell delay = 2.323 ns ( 38.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.671 ns ( 61.24 % ) " "Info: Total interconnect delay = 3.671 ns ( 61.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.994 ns" { CLK Clock Clock~clkctrl count:Cnt|y.00000 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "5.994 ns" { CLK {} CLK~combout {} Clock {} Clock~clkctrl {} count:Cnt|y.00000 {} } { 0.000ns 0.000ns 1.044ns 1.596ns 1.031ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { CLK CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 {} } { 0.000ns 0.000ns 0.113ns 0.970ns } { 0.000ns 0.999ns 0.000ns 0.661ns } "" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.994 ns" { CLK Clock Clock~clkctrl count:Cnt|y.00000 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "5.994 ns" { CLK {} CLK~combout {} Clock {} Clock~clkctrl {} count:Cnt|y.00000 {} } { 0.000ns 0.000ns 1.044ns 1.596ns 1.031ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "part6.v" "" { Text "C:/altera/72sp2/LAB8/part6/part6.v" 133 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.035 ns + " "Info: + Micro setup delay of destination is 0.035 ns" {  } { { "db/altsyncram_p592.tdf" "" { Text "C:/altera/72sp2/LAB8/part6/db/altsyncram_p592.tdf" 41 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.148 ns" { count:Cnt|y.00000 count:Cnt|WideOr1~109 count:Cnt|WideOr0~64 Address_in[4]~224 myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "4.148 ns" { count:Cnt|y.00000 {} count:Cnt|WideOr1~109 {} count:Cnt|WideOr0~64 {} Address_in[4]~224 {} myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 {} } { 0.000ns 0.770ns 0.460ns 0.452ns 1.631ns } { 0.000ns 0.150ns 0.393ns 0.150ns 0.142ns } "" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { CLK CLK~clkctrl myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { CLK {} CLK~combout {} CLK~clkctrl {} myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram1|ram_block4a0~porta_address_reg5 {} } { 0.000ns 0.000ns 0.113ns 0.970ns } { 0.000ns 0.999ns 0.000ns 0.661ns } "" } } { "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.994 ns" { CLK Clock Clock~clkctrl count:Cnt|y.00000 } "NODE_NAME" } } { "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72sp2/quartus/bin/Technology_Viewer.qrui" "5.994 ns" { CLK {} CLK~combout {} Clock {} Clock~clkctrl {} count:Cnt|y.00000 {} } { 0.000ns 0.000ns 1.044ns 1.596ns 1.031ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}